The current MBE multiplier and Baugh-wooley multipliers perform multiplication only in signed numbers. Therefore, this paper presents the design and implementation of the modified cabin multiplier without signature. The MBE circuit generates half of the parallel products. Extending the sign bit of the operands and generating an additional partial product gives the SUMBE multiplier. The carry save adder (CSA) tree and the carry look ahead adder used to accelerate the operation of the multiplier. Since the signed and unsigned multiplication operation is performed by the same multiplier unit. Therefore, the required hardware and chip area reduce and, in turn, reduce power dissipation and cost.
Multipliers are key components of many high-performance systems, such as microprocessors, digital signal processors, etc. Speed optimization and multiplier area is a major design problem that is often a conflicting constraint, so that speed improvement results mainly in larger areas. We propose an architecture designed by VHDL based on the algorithm of multiplication of cabins, that not only optimizes the speed but also is efficient in the use of energy.