01-12-2012, 05:39 PM
3-D (IC)chip technology
3D_IC-final.ppt (Size: 2.04 MB / Downloads: 33)
3-D Chip Design Challenges
The need to pack more transistors into a single package is becoming a needed necessity. There’s a big demand, in the consumer market, for smaller packages and in order to meet this demand, 3-D chip technology must be perfected.
To maintain the overall pace according to Moore’s law requires an acceleration of packaging development companies have driven 3D packaging envelopment in the past few years but thermal aspects and high density interconnects have been neglected in those applications. While 2D scaling has been used in high performance processors over several decades, the third dimension has not yet been tackled.
3-D chip technology
Oxide Material
For 40 years, the SiO2 gate oxide combined materials for scaling MOS devices down to the 90nm technology node.
Starting with the 90nm technology, SiO2 has been replaced by SiON dielectric, which features a higher permittivity and consequently improves the device performances while keeping the parasitic leakage current within reasonable limits.
Starting with the 45-nm technology, leakage reduction has been achieved through the use of various high-K dielectrics such as Tantalum Oxide Ta2O5 (er=25) or Titanium Oxide TiO2 (er=40).
This provides much higher device performance as if the device was fabricated in a technology using conventional SiO2 with much reduced “equivalent SiO2 thickness”.
The high-k transistors feature outstanding current switching capabilities together with low leakage..
Advantages
The 3D chip design technology can be exploited to build SoCs by placing circuits with different voltage and performance requirements in different layers.
The 3D integration can reduce the wiring ,thereby reducing the capacitance, power dissipation and chip area and therefore improve chip performance.
Additionally the digital and analog components in the mixed-signal systems can be placed on different Si layers thereby achieving better noise performance due to lower electromagnetic interference between such circuits blocks.
From an integration point of view, mixed-technology assimilation could be made less complex and more cost effective by fabricating such technologies on separate substrates followed by physical bonding.
Conclusion
3D ICs are an attractive chip architecture, that can alleviate inter connect related problems such as delay and power dissipation and can also facilitate integration of heterogeneous technologies in one chip. The multilayer chip building technology opens up a whole new world of design like a city skyline transformed by skyscrapers, the world of chips may never look at the same again.