07-11-2012, 04:32 PM
3-D ICs
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INTRODUCTION
There is a saying in real estate; when land get expensive, multi-storied buildings are the alternative solution. We have a similar situation in the chip industry. For the past thirty years, chip designers have considered whether building integrated circuits multiple layers might create cheaper, more powerful chips.
Performance of deep-sub micrometer very large scale integrated (VLSI) circuits is being increasingly dominated by the interconnects due to increasing wire pitch and increasing die size. Additionally, heterogeneous integration of different technologies on one single chip is becoming increasingly desirable, for which planar (2-D) ICs may not be suitable.
The three dimensional (3-D) chip design strategy exploits the vertical dimension to alleviate the interconnect related problems and to facilitate heterogeneous integration of technologies to realize system on a chip (SoC) design. By simply dividing a planar chip into separate blocks, each occupying a separate physical level interconnected by short and vertical interlayer interconnects (VILICs), significant improvement in performance and reduction in wire-limited chip area can be achieved.
In the 3-Ddesign architecture, an entire chip is divided into a number of blocks, and each block is placed on a separate layer of Si that are stacked on top of each other.
MOTIVATION FOR 3-D ICs
The unprecedented growth of the computer and the information technology industry is demanding Very Large Scale Integrated ( VLSI ) circuits with increasing functionality and performance at minimum cost and power dissipation. Continuous scaling of VLSI circuits is reducing gate delays but rapidly increasing interconnect delays. A significant fraction of the total power consumption can be due to the wiring network used for clock distribution, which is usually realized using long global wires.
Furthermore, increasing drive for the integration of disparate signals (digital, analog, RF) and technologies (SOI, SiGe, GaAs, and so on) is introducing various SoC design concepts, for which existing planner (2-D) IC design may not be suitable.
INTERCONNECT LIMITED VLSI PERFORMANCE
In single Si layer (2-D) ICs, chip size is continuously increasing despite reductions in feature size made possible by advances in IC technology such as lithography and etching. This is due to the ever growing demand for functionality and high performance, which causes increased complexity of chip design, requiring more and more transistors to be closely packed and connected. Small feature sizes have dramatically improved device performance. The impact of this miniaturization on the performance of interconnect wire, however, has been less positive. Smaller wire cross sections, smaller wire pitch, and longer line to traverse larger chips have increase the resistance and capacitance of these lines, resulting in a significant increase in signal propagation (RC) delay. As interconnect scaling continues, RC delay is increasingly becoming the dominant factor determining the performance of advanced IC’s.
PHYSICAL LIMITATIONS OF Cu INTERCONNECTS
At 250 nm technology node, Cu with low-k dielectric was introduced to alleviate the adverse effect of increasing interconnect delay.However,below 130nm technology node, substantial interconnect delays would result in spite of introducing these new materials, which in turn will severely limit the chip performance. Further reduction in interconnect delay is not possible.
This problem is especially acute for global interconnects, which comprise about 10% of total wiring in current architectures. Therefore, it is apparent that material limitations will ultimately limit the performance improvement as technology scales. Also, the problem of long lossy lines cannot be fixed by simply widening the metal lines and by using thicker interlayer dielectric, since this will leas to an increase in the number of metal layers. This will result in an increase in complexity, reliability and cost.
SYSTEM – ON – A – CHIP DESIGN
System – on – a –chip (SoC) is a broad concept that refers to the integration of nearly all aspects of a system design on a single chip. These chips are often mixed-signal and/or mixed-technology designs, including such diverse combinations as embedded DRAM, high – performance and low-power logic, analog, RF, programmable platforms (software, FPGAs, Flash, etc.).
SoC designs are often driven by the ever-growing demand for increased system functionality and compactness at minimum cost, power consumption, and time to market. These designs form the basis for numerous novel electronic applications in the near future, in areas such as wired and wireless multimedia communications including high speed internet applications, medical applications including remote surgery, automated drug delivery, and non invasive internal scanning and diagnosis, aircraft/automobile control and safety, fully automated industrial control systems, chemical and biological hazard detection, and home security and entertainment systems, to name a few.
ADVANTAGES OF 3D ARCHITECTURE
The 3D architecture offers extra flexibility in system design, placement and routing. For instance, logic gates on a critical path can be placed very close to each other using multiple active layers. This would result in a significant reduction in RC delay and can greatly enhance the performance of logical circuits.
• The 3D chip design technology can be exploited to build SoCs by placing circuits with different voltage and performance requirements in different layers.
• The 3D integration can reduce the wiring ,thereby reducing the capacitance, power dissipation and chip area and therefore improve chip performance.
• Additionally the digital and analog components in the mixed-signal systems can be placed on different Si layers thereby achieving better noise performance due to lower electromagnetic interference between such circuits blocks.
• From an integration point of view, mixed-technology assimilation could be made less complex and more cost effective by fabricating such technologies on separate substrates followed by physical bonding.
Increasing Chip Area and Performance
3-D IC performance can be enhanced to exceed the performance of 2-D ICs by improving interconnect delay. This is achieved by increasing the wire pitch, which causes a reduction in the resistance. The effect of increasing psemi and pglobal on the operating frequency and Ac.
This illustrates how the optimum semi global pitch (i.e., the psemi associated with the minimum Ac) increases to obtain higher operating frequencies. Also, as the semi global tier pitch increases, chip area and, therefore, interconnect length also increases. However, we can see that the increase in chip area still remains well below the area required for the 2-D case. The figure also helps defines a maximum – performance 3-D chip – a chip with the same area as the corresponding 2-D chip, which can be obtained by increasing the semi global pitch beyond that for the 4-GHz case.
Two scenarios are considered 1) global pitch is increased to match the global pitch for the 2-d case and 2) global pitch is increased to match the chip area (footprint) for the 2-d case. Note that the delay requirements sets a maximum values of interconnect length are given tier. Therefore, as interconnect lengths are increased, lines which exceed this maximum length criterion for that particular tier need to be rerouted on upper ties.