15-09-2016, 12:14 PM
1454596524-3D.ppt (Size: 626.5 KB / Downloads: 7)
Motivation
Interconnect structures increasingly consume more of the power and delay budgets in modern design
Plausible solution: increase the number of “nearest neighbors” seen by each transistor by using 3D IC design
Smaller wire cross-sections, smaller wire pitch and longer lines to traverse larger chips increase RC delay.
RC delay is increasingly becoming the dominant factor
At 250 nm Cu was introduced alleviate the adverse effect of increasing interconnect delay.
130 nm technology node, substantial interconnect delays will result
Timing
In current technologies, timing is interconnect driven.
Reducing interconnect length in designs can dramatically reduce RC delays and increase chip performance
The graph below shows the results of a reduction in wire length due to 3D routing
Discussed more in detail later in the slides
Energy performance
Wire length reduction has an impact on the cycle time and the energy dissipation
Energy dissipation decreases with the number of layers used in the design
Following graphs are based on the 3D tool described later in the presentation