24-12-2012, 05:43 PM
8 bit analog to digital converters with differential inputs
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description
The ADC0804 is a CMOS 8-bit successive-approximation analog-to-digital converter that uses a modified
potentiometric (256R) ladder. The ADC0804 is designed to operate from common microprocessor control
buses, with the 3-state output latches driving the data bus. The ADC0804 can be made to appear to the
microprocessor as a memory location or an I/O port. Detailed information on interfacing to most popular
microprocessors is readily available from the factory.
A differential analog voltage input allows increased common-mode rejection and offset of the zero-input analog
voltage value. Although REF/2 is available to allow 8-bit conversion over smaller analog voltage spans or to
make use of an external reference, ratiometric conversion is possible with REF/2 open. Without an external
reference, the conversion takes place over a span from VCC to ANLG GND. The ADC0804 can operate with
an external clock signal or, with an additional resistor and capacitor, can operate using an on-chip clock
generator.
PRINCIPLES OF OPERATION
The ADC0804 contains a circuit equivalent to a 256-resistor network. Analog switches are sequenced by
successive-approximation logic to match an analog differential input voltage (VI+ − VI−) to a corresponding tap on
the 256-resistor network. The most significant bit (MSB) is tested first. After eight comparisons (64 clock periods),
an 8-bit binary code (1111 1111 = full scale) is transferred to an output latch and the interrupt (INTR) output goes low.
The device can be operated in a free-running mode by connecting the INTR output to the write (WR) input and holding
the conversion start (CS) input at a low level. To ensure startup under all conditions, a low-level WR input is required
during the power-up cycle. Taking CS low anytime after that will interrupt a conversion in process.
When WR goes low, the ADC0804 successive-approximation register (SAR) and 8-bit shift register are reset. As long
as both CS and WR remain low, the ADC0804 remains in a reset state. One to eight clock periods after CS or WR
makes a low-to-high transition, conversion starts.
When CS and WR are low, the start flip-flop is set and the interrupt flip-flop and 8-bit register are reset. The next clock
pulse transfers a logic high to the output of the start flip-flop. The logic high is ANDed with the next clock pulse, placing
a logic high on the reset input of the start flip-flop. If either CS or WR have gone high, the set signal to the start flip-flop
is removed, causing it to be reset. A logic high is placed on the D input of the 8-bit shift register and the conversion
process is started. If CS and WR are still low, the start flip-flop, the 8-bit shift register, and the SAR remain reset. This
action allows for wide CS and WR inputs with conversion starting from one to eight clock periods after one of the inputs
goes high.
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