08-10-2012, 01:45 AM
Low power digital multiplier designs are based on row bypassing techniques which are mainly used to reduce the switching power dissipation, by using Xilinx 9.1 ISE tool.
The proposed method produce an effective results when compare to array and conventional multipliers.
The reduction in resources like delay, power consumption, area and PDP can be accomplished.
To minimize power consumption in digital multipliers.
To reduce the power delay product(PDP) and delay.
To achieve high speed.
To reduce the chip area and power dissipation.[/font]