An 8-bit Vedic multiplier is improved in terms of transmission delay when compared to extra predictable multipliers. We have used 8-bit barrel shifter that craves for a single clock cycle for 'n' number of changes in our projected design. The arrangement is implemented and tested using FPGA and ISE Simulator. The central part was implemented in Xilinx Spartan-6 family xc6s1x75T-3-fgg676 FPGA. The transmission delay contrast was extracted from the synthesis report and from the static timing report as well. The structural design could achieve propagation delay of 6.781ns by means of the barrel displacer in the base and multiplier selection module.
A multiplier is one of the key hardware blocks in most applications, such as encryption and decryption algorithms for digital signal processing in cryptography and other logical calculations. With the next technology, many researchers tried to design multipliers that offered any of the factors of high speed, low power consumption, design regularity and less area or even grouping of the three in multiplier. The multiplier is the core component of any DSP application, and therefore the processor speed depends greatly on the multiplier design. Since multiplication dominates the execution time of most DSP algorithms, so there is a need for high-speed multiplier. Currently, the multiplication time is the dominant factor in the configuration of the instruction cycle time of a DSP chip.