21-05-2012, 05:15 PM
8085 INTRODUCTION
8085 INTRODUCTION.ppt (Size: 1.51 MB / Downloads: 20)
The features of INTEL 8085 are :
It is an 8 bit processor.
It is a single chip N-MOS device with 40 pins.
It has multiplexed address and data bus.(AD0-AD7).
It works on 5 Volt dc power supply.
The maximum clock frequency is 3 MHz while minimum frequency is 500kHz.
It provides 74 instructions with 5 different addressing modes.
It provides 16 address lines so it can access 2^16 =64K bytes of memory.
It generates 8 bit I/O address so it can access 2^8=256 input ports.
It provides 5 hardware interrupts:TRAP, RST 5.5, RST 6.5, RST 7.5,INTR.
It provides Acc ,one flag register ,6 general purpose registers and two special purpose registers(SP,PC).
It provides serial lines SID ,SOD.So serial peripherals can be interfaced with 8085 directly
8085 PIN DESCRIPTION
READY:This an output signal used to check the status of output device.If it is low, µP will WAIT until it is high.
TRAP:It is an Edge triggered highest priority , non mask able interrupt. After TRAP, restart occurs and execution starts from address 0024H.
RST5.5,6.5,7.5:These are maskable interrupts and have low priority than TRAP.
INTR¯&INTA:INTR is a interrupt request signal after which µP generates INTA or interrupt acknowledge signal.
IO/M¯:This is output pin or signal used to indicate whether 8085 is working in I/O mode(IO/M¯=1) or Memory mode(IO/M¯=0 ).
ARITHMETIC GROUP
DAD Rp (Add specified register pair with HL pair)
ExampleAD D.(Add the content of E with L and that of D with H register and result in HL pair)
Suppose the content of HL pair is H=20H ,L=40H and DE pair is D=30H, E=10H.
Initially After execution
H=20H ,L=40H H=50H ,L=50H
D=30H, E=10H D=30H, E=10H
Flags Affected :Only carry flag is modified.
Addressing mode: Register.
STACK AND MACHINE CONTROL
XTHL (Exchange HL register pair contents with top of stack).
Example:XTHL(Exchange top with HL pair).
Suppose at HL pair the data is H= 20H,L= 30H & SP =FFH
& at locations FF=10H and at FFFE= 80H.
Initially After execution
H=20H,L=30H H=10H,L=80H.
SP=FF =10H,FFFE=80H FFFD=20H,FFFE=30H
Flags Affected :No flags affected.
Addressing mode: Register indirect
TIMING AND STATE DIAGRAM
Memory Read Cycle: It basically requires 3T states from T1-T3 .
The ALE pin goes high at first T state always.
AD0-AD7 are used to fetch data from memory and store the lower byte of address.
A8-A15 store the higher byte of the address while IO/M¯ will be low since it is memory related operation.
RD¯ will only be low at the data fetching time.
WR¯ will be at HIGH level since no write operation is done.
S0=0,S1=1 for Memory read cycle.