02-10-2012, 04:41 PM
8259A PROGRAMMABLE INTERRUPT CONTROLLER
21262738-8259a-Programmable-Interrupt-Controller-2.ppt (Size: 1.08 MB / Downloads: 51)
NEED FOR 8259A
8085 Processor has only 5 hardware interrupts.
Consider an application where a number of I/O devices connected with CPU desire to transfer data using interrupt driven data transfer mode. In this process more number of interrupt pins are required.
In these multiple interrupt systems the processor will have to take care of priorities.
8259A PIC- FEATURES
Manage 8 interrupts according to the instructions written into the control registers.
Vector an interrupt request anywhere in the memory map. However all the 8 interrupts are spaced at an interval of four to eight locations.
Resolve 8 levels of interrupt priorities in variety of modes.
Mask each interrupt request individually.
Read the status of pending interrupts, in-service interrupts and masked interrupts.
8259A PIC- INTERRUPTS AND CONTROL LOGIC SECTION
This register can be programmed by an OCW to store the bits which mask specific interrupts.
IMR operates on the IRR.
An interrupt which is masked by software (By programming the IMR) will not be recognized and serviced even if it sets corresponding bits in the IRR.
8259A- OPERATING MODES
AUTOMATIC EOI:
In this mode, no command is necessary.
During the third interrupt acknowledge cycle, the ISR bit is reset.
DRAWBACK: The ISR does not have information about which ISR is being serviced. Thus, any IR can interrupt the service routine, irrespective of its priority, if the interrupt enable FF is set.