05-09-2012, 04:37 PM
A 26 GHz Phase-Locked Loop Frequency Multiplier in 0.18-μm CMOS
A 26 GHz Phase-Locked.pdf (Size: 2.5 MB / Downloads: 63)
Abstract
This thesis presents the analysis, design and characterization of an integrated highfrequency
phase-locked loop (PLL) frequency multiplier. The frequency multiplier is
novel in its use of a low multiplication factor of 4 and a fully differential topology for
rejection of common mode interference signals. The PLL is composed of a voltage
controlled oscillator (VCO), injection-locked frequency divider (ILFD) for the first
divide-by-two stage, a static master-slave flip-flop (MSFF) divider for the second
divide-by-two stage and a Gilbert cell mixer phase detector (PD). The circuit has
been fabricated using a standard CMOS 0.18-μm process based on its relatively low
cost and ready availability. The PLL frequency multiplier generates an output signal
at 26 GHz and is the highest operational frequency PLL in the technology node
reported to date.
Time domain phase plane analysis is used for prediction of PLL locking range
based on initial conditions of phase and frequency offsets. Tracking range of the PLL
is limited by the inherent narrow locking range of the ILFD, and is confirmed via
experimental results.
Introduction
The demand for increased data rates in communication systems as well as applications
such as automotive radar are driving the operational requirements of circuits
and systems to higher frequencies. At the same time there is pressure to bring the
cost of new technologies down to allow a greater uptake by end users. Increased
levels of integration are being used to reduce the cost of cost-sensitive applications.
Through continued refinement of its processes, complementary metal-oxide semiconductor
(CMOS) technology now has the capability of operating in the tens of gigahertz
range. CMOS technology is used extensively for computer and memory integrated
circuit (IC) fabrication and is well-suited to high levels of integration, making it an
ideal candidate for high-volume low-cost applications.
As operational frequencies increase the challenge of signal generation also increases.
High frequency signals may be generated by using low frequency oscillators
and converting them to higher frequencies using frequency multiplier circuits. CMOS
frequency doublers have been reported recently up to 75 GHz [1], [2].
Selected Review of PLL Performance
A 5 GHz WLAN receiver in 0.24-μm CMOS using a PLL-based frequency synthesizer
was reported in 2000 [4]. The PLL in the paper synthesized frequencies between 4.84
and 4.994 GHz, using a reference input frequency of 11 MHz and a loop bandwidth
of 280 kHz. Out-of-band phase noise was measured at -101 dBc/Hz at 1 MHz offset.
A multiple-output frequency synthesizer with very low jitter performance using
a PLL-generated 2.4 GHz signal as the basic clock source has been developed [5].
The core PLL employed a 25 MHz crystal oscillator as the reference clock, with a
phase-frequency detector, high-swing cascode charge pump with programmable output
current for UP-DOWN mismatch compensation and setting of loop bandwidth,
high speed prescalers, a 200 MHz low-jitter output and the feedback divider. Fig. 2.1
shows the frequency synthesizer block diagram.
PLL Operation
A PLL may be described as a linear feedback system that compares the system output
phase generated by a voltage controlled oscillator (VCO) with an input reference
phase using a phase comparator or detector (PD). A difference in phase between the
output RF signal and the input reference signal generates an error voltage that, after
filtering by a loop/lowpass filter (LPF), is used to change the frequency/phase of the
VCO in such a way that the error is minimized, leading to a locked state.
Time Domain Analysis
Analysis of PLLs is often carried out under the assumption that the loop is considered
linear. This assumption will be true for cases where the input reference signal and the
VCO-derived internal signal are close to lock. For cases where the input reference and
VCO are not close to lock, a non-linear solution provides useful insight into the locking
mechanism in the time domain. Viterbi [48] examines the time domain solution for a
non-linear PLL response. The analysis presented here follows his work for the PLL
configuration being considered. A solution to the non-linear PLL loop equation using
phase plane analysis will provide insight into the determination of locking range for
the PLL.