17-04-2014, 03:15 PM
A 45nm CMOS, low jitter, all-digital delayed locked loop with a circuit to dynamically vary phase to achieve fast lock
Abstract
The objective of the thesis is to address the problem of clock skew between two different clock
domains in modern day microprocessors due to the process, voltage and temperature (PVT)
variations. In order to mitigate the misalignment of the clocks in the different clock domains, a
delay line is added in all but the reference clock domain. These delay lines add or subtract the
delay (as necessary) to keep the clocks continuously aligned to a common reference clock delay.
This ensures error free data transfer between any two clock domains.
A novel Digital DLL design is proposed to achieve short locking time by having a separate
circuitry for fast lock in the DLL. The fast lock mechanism can be switched off and the power
dissipation can be returned to normal levels after the DLL has locked. A separate fine-delay
block makes the proposed DLL have ultra-low jitter after lock. The results show that the
proposed DLL, implemented in 45nm CMOS technology, needs only 24 cycles to correct (i.e. to
lock) for 500ps clock skew when compared to more than 38 lock cycles for a conventional DLL
without the fast lock mechanism. A Monte-Carlo simulation yielded a RMS jitter and peak-
to-peak jitter values after lock of 5.26ps and 10.57ps respectively. Average power consumption
before lock is <425μW with this number falling to <335μW after lock. The frequency of
operation of the proposed DLL is 280MHz - 1.63GHz and can be used for a variety of applications
which require precise time intervals.
Introduction
Modern day microprocessors have multiple clock domains with each clock domain being re-
stricted to a block. At any instance in time, some of them are powered down (to minimize
power dissipation) while some of them are up and running depending on the scenario of opera-
tion. They are always supplied by the same Phase locked loop (PLL) [8]. Figure 1.1 shows the
clock distribution in a microprocessor.
Delay Locked Loop Overview
The reduction of clock skew is one of the important problems in the VLSI design. DLLs are used
in VLSI circuits in order to decrease clock screw in the clock networks. DLL is a feedback system
that aligns the feedback clock to the reference clock. This is done by delaying the input feedback
clock after passing it through a delay line and controlling the delay using the control mechanism.
Once the input feedback clock is delayed, a phase detector (PD) compares the phases of the two
inputs. Based on PD output value, the delay is adjusted (increased or decreased) until the two
phases are aligned. A DLL is widely used as a timing circuit in many systems for the purpose
of clock generation [9], [10], signal synchronization [11], and others [12]. For example, a DLL is
able to provide multiple clock signals which are separated from each other by a well-controlled
phase shift (delay). This application of DLL is widely used in DDR memory circuits to align the
DQS strobe in the middle of the data eye DQ. When appropriate logic, such as edge combining
is used, a new clock signal which is of a different frequency can be generated by the DLL.
Such an application of a DLL has been reported in [13] for personal communication services
(PCS). Another application of a DLL is for the purpose of clock deskewing in synchronous data
transfer among communication chips.
Comparison between Analog DLL and Digital DLL
An analog DLL is a complex analog circuit requiring process-specific implementation. Scaling
of analog integrated circuits directly affects output resistance and intrinsic gain of the circuit.
As we cross below the 100nm mark, the design of these analog circuits becomes quite exigent,
especially for low supply voltages around 1 V. This results in higher power consumption and
enhanced design complexity. [25]. So, it is not practical to reuse the same design for different
technology, making analog DLL a non-portable architecture. Analog DLL generally provides
better jitter performance at the expense of greater complexity [24]. Analog DLLs are more
susceptible to process variations and less immune from power-supply noise because of smaller
noise margins. In an analog DLL, if the low pass filter has less capacitor value then this will
result in more jitter and thus providing more variation in Voltage controlled delay line.
Conclusion
In this chapter general information about DLL and the types of DLL is described. The ad-
vantages and disadvantages of the Analog and Digital DLL are also discussed. The common
requirements for the design of a DLL are short locking time, low jitter performance, less power
consumption, small area and less phase error after lock or minimum time of resolution.
In the next chapter, a detailed discussion of the design of a Digital DLL is given.