09-08-2012, 11:34 AM
A BiCMOS Dynamic Multiplier Using Wallace Tree Reduction
Architecture
A BiCMOS Dynamic Multiplier Using Wallace.pdf (Size: 333.16 KB / Downloads: 34)
Introduction
High-speed multipliers are usually realized by parallel
architectures [l], where Wallace reduction structure
[1][2] and carry look ahead circuit have been used
to enhance the speed performance. In a high-speed
parallel multiplier using Wallace tree reduction structure,
the most important building cells are the full
adder circuit and the carry look-ahead circuit. Although
CMOS dynamic technique [2][3] can provide
a speed advantage over the static one for implementing
serial adders, it’s not suitable for realizing the full
adder circuit for parallel multipliers using Wallace tree
reduction structure due to race problems [3]. Currently,
BiCMOS static logic circuits have been proved
to be helpful for realizing high-speed VLSI systems [4].
In fact, BiCMOS dynamic logic circuits can also be
very helpful for implementing high-speed digital systems.
Recently, a BiCMOS dynamic carry look ahead
circuit, which is built by cascading BiCMOS dynamic
logic gates without race problems, has been reported
[5]-[8]. However, it’s for 5V operation.
The BiCMOS Dynamic Multiplier
High-speed parallel multipliers with Wallace tree
reduction structure have been realized by CMOS
static circuits [2] but they suffer from the speed
penalty as a result of complex routing, long wiring,
irregular layout of the architecture [Z]. Due to race
problems, CMOS dynamic circuits are not suitable
for building high-speed parallel multipliers with Wallace
tree reduction structure. In fact, the BiCMOS
dynamic circuits are appropriate for implementing
Wallace tree reduction architecture with complicated
wiring. In order to show the versatilities of the BiCMOS
dynamic full adder circuit for constructing parallel
multipliers with Wallace tree reduction structure,
an 8x8 parallel multipliers as shown in Fig. 3
has been designed. Fig. 4 shows the layout of the
BiCMOS dynamic 8x8 parallel multipliers using Wallace
tree reduction architecture. The die area is
3144pm x 1455pm. A large portion of the space is
allocated for the complex routing, long wiring and irregular
layout for realizing the Wallace tree reduction
architecture.
Conclusion
This paper presents a BiCMOS dynamic multiplier,
which is free from race and charge sharing problems,
using Wallace tree reduction architecture and 1.5V
full-swing BiCMOS dynamic logic circuit. A 1.5V 8x8
multiplier, which is designed based on a 1pm BiC
MOS technology, shows a 2 . 3 i~m provement in speed
as compared to the CMOS static one.