07-07-2012, 02:43 PM
A CPLD VHDL Introduction
A CPLD VHDL Introduction.PDF (Size: 332.89 KB / Downloads: 19)
Introduction
VHDL, an extremely versatile tool developed to aid in many aspects of IC design, allows a user
to structure circuits in many levels of detail. This versatility also makes the job of the VHDL
synthesis tool a lot more complex, and there is latitude for interpretation depending on the
VHDL coding style. One synthesis tool may implement the same code very differently from
another. In order to achieve the best results using VHDL, the designer should work at the
Register Transfer Level (RTL).
Although working at the RTL for designs may be more time-consuming, all major synthesis
tools on the market are capable of generating a clear cut implementation of designs for CPLDs
at this level. Using higher levels of abstraction may give adequate results, but tend to be less
efficient. Additionally, by expressing designs in this manner, the designer also gains the ability
to port VHDL designs from one synthesis tool to another with minimal effort. The following
examples will show designers the best design practices when targeting Xilinx XC9500XL,
XC9500XV and CoolRunnerTM XPLA3 families.
HDL coding style
There are many ways of modeling the same state machine. HDL code may be partitioned into
three different portions to represent the three parts of a state machine (next state logic, current
state logic, and output logic). It may also be structured so that the three different portions are
combined in the model. For example, current state and next state logic may be combined with
separate output logic, as shown in example FSM1; or next state and output logic may be
combined with a separate current state logic, as shown in example FSM2. However, in VHDL,
it is impossible to synthesize a combined current state, next state, and output logic in a single
always statement.
Mealy or Moore type outputs
There are generally two ways to describe a state machine – Mealy and Moore. A Mealy state
machine has outputs that are a function of the current state and primary inputs. A Moore state
machine has outputs that are a function of the current state only, and so includes outputs direct
from the state register. If outputs come direct from the state register only, there is no output
logic.
The examples below show the same state machine modeled with a Mealy or Moore type
output. A state diagram is also associated with each of the two examples.