26-05-2012, 04:34 PM
A Different Approach to Fabricating Three-Dimensional Integrated Circuits
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Abstract
This work presents a new fabrication technology for
three-dimensional integration. In 3D integrated
circuits, transistors may be constructed on different
device layers. Transistors are then wired to other
transistors on the same layer using conventional wiring
or to other transistors on another layer using vertical
wiring. The proposed technology consists of fabricating
n-type and p-type transistors each on a separate device
layer using conventional 2D fabrication technology and
then combine the two device layers with inter-wafer
interconnect. The new proposed technology is capable
of providing improvement for integrated circuits in
total wire length and chip area, as well as easing chip
design phase and eliminating chip latch-up problem.
Introduction
3D integrated circuits refer to the fabrication of any
single chip with multiple device layers stacked over
each others. This is achieved by bonding multiple
wafers using special inter-layer vias to achieve
interconnections of the vertically staked chips.
Different approaches for fabricating 3D integrated
circuits are available. In these approaches, cells of the
3D IC exist in a single device layer and vertical wiring
is used to connect cells belonging to different layers.
The main objective of these approaches is to lower the
overall interconnect length by using vertical wiring. In
particular, existing 3D integration technologies make
use of vertical wiring to reduce the maximum length of
interconnects and the number of long interconnects.
Proposed 3D IC Fabrication Technology
In this section, a different approach to manufacturing
3D integrated circuits is proposed and the motivation
for the work is presented.
2.1. Overview
There are many types of fabrication defects that are
likely to occur while the chip is being manufactured.
Design rules are formulated to minimize the probability
of these defects to occur and make the production of
faultless chips reach an acceptable level.
Design rules form constraints on minimizing the
layout area. These rules differ from one fabrication
technology to the other. However, the most limiting
design rule for all technologies that allow the
fabrication of n-type and p-type transistors on the same
substrate is the isolation distance, which forces a
minimum separation between n-diffusion and pdiffusion.
For instance, in SCMOS technology, the
isolation distance is of at least 10 i.e. 5 times the
minimum feature size allowed by the lithographic
printing. In CMOS circuits, this separation represents
an unexploited region, only a part of it is infrequently
used for intra-cell wire routing. This fact was the main
motivation for finding a solution to this problem.
Advantages of Proposed Technology
In addition to the advantage of yield enhancement
common for all 3D integration because of the reduced
die size, the proposed 3D integration technology has the
following advantages.
3.1. Reducing Chip Area
As mentioned earlier, when the proposed technology
is used, the area separating n-type and p-type diffusions
is completely eliminated. So, cell heights are reduced
and consequently chip area is diminished.
Conclusion
Three-dimensional integrated circuits are expected to
offer significant benefits over conventional twodimensional
integrated circuits. A number of 3D
integration fabrication technologies are already
available. This paper presents a different approach to
fabricating 3D integrated circuits and illustrates some
of the potentials, challenges, and feasibility of this
method.
In addition, the paper offers solutions to the layout
design of the new technology, as well as placement and
routing tools for these circuits. Using these tools,
performance results of ICs using the proposed 3D
technology are analyzed. Improvement of 8.7% to 33%
in overall wire length and 44% to 51.7% in chip area
are observed.