22-03-2013, 03:24 PM
A Fast Resolving BiNMOS Synchronizer for Parallel Processor Interconnect
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Abstruct
The design, testing, and application of a BiNMOS
metastability resolving synchronizer is described. High speed
signaling requires multiple clock cycle metastability settling time.
The integrated circuit provides low tau (fast resolution) and is
considered one of the fastest synchronizers available to date. The
circuit reduces metastability failure with a high gain-bandwidth
product and longer settling time per clock cycle. High gainbandwidth
product is accomplished with n-p-n transistors driving
a cross-coupled inverter latch with reduced node capacitance.
Longer settling time is provided by omitting metastability immune
circuitry and using a parallel staged synchronizer.
INTRODUCTION
TH IS paper describes a synchronizer developed for mas- sively parallel processor interconnect. Each processor
node has a separate nonsynchronized clock. Synchronizer
parameters have been optimized to provide fast metastability
resolution in order to reduce latency while increasing
metastability settling time. Digital systems are becoming more
complex and integrated. Synchronizer applications were once
satisfied with discrete IC components but now many applications
require that the synchronizer be incorporated as part of a
larger component such as a niicroprocessor or communication
component to meet the need5 of high speed clocks.
A synchronizer embedded in large VLSI components must
be tested properly and MTBF must be established without
doubt. The errors caused by metastable behavior are particularly
difficult to trace due to their random and intermittent
nature. They may be the cause of many unexplained computer
crashes and other mysterious digital system malfunctions 191,
[I 71. They may also be blamed for unrelated random failures.
In systems designed for high reliability.
DESIGN
The design is broken into sections involving establishing the
probability of failure. omitting metastability immune circuitry.
increasing the settling time per clock cycle, and improving the
gain-bandwidth product.
A. Estublishing Prohuhilitj oj Fuilure
In a truly asynchronous interface, the possibility of metastability
failure is always present. Some may think that the
metastability problem can be solved by a system-level design.
but every solution is only a shift of the problem from one
circuit to another circuit [2]. However, the probability of
metastability failure can be reduced to an acceptable level.
Metastability mean-time-between-failure or MTBF is typically
increased by decreasing the sampling rate [3], [9], [ 111.
Unfortunately decreasing the sampling rate directly increases
the latency of data through the synchronizer. Therefore it is
preferred to maximize the settling time for ;I given sampling
rate. Settling time is the time allowed for a synchronized signal
to remain at rest before being evaluated.
Oniissiori of’ Metcistrihle Irnriiirrie Circuitry
The synchronizer does not contain metastable immune circuitry.
Metastable immune latches do not change output state
until metastability has resolved in order to prevent an invalid
signal (other than O/I ) from propagating to another stage.
The metastable immune latch. however. does not provide a
stable output any sooner nor (within a bounded amount of
time) provide a better defined binary than a nonimmune latch.
In fact, the immune circuitry usually slows down the output
resolution and requires a longer settling timi: to provide the
same MTBF as a nonimmune synchronizer. Omission of the
immune circuitry provides more settling time for a given
number of clock cycles and exponentially increases the MTBF.
CONCLUSION
We have discussed the design, testing, and application of
a BiNMOS synchronizer. The synchronizer has increased
settling time per clock cycle due to parallel synchronizer
stages without metastable immune circuitry. It also has fast
metastability resolution due to reduced node capacitance with
an n-p-n transistor forcing a jamb latch. The synchronizer
has a r of 70 ps, and is considered to have one of the
fastest resolutions documented. MTBF calculation is based on
parameters which are easy to validate as well as simulate.
Testing is accomplished with histograms collected with continuous
evaluation. Validation results are compared and agree
well with simulations. The synchronizer is used in high speed
asynchronous data transmission such as massively parallel
processor interconnect.