05-09-2012, 01:48 PM
A Low Power Structure Design of 2D-LFSR and Encoding Technique for BIST
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Abstract
BIST is a design technique that allows a circuit to test itself. The technique can provide
shorter test time compared to an externally applied test and allows the use of low-cost test
equipment during all stages of production. Due to the randomness properties of Linear
Feedback Shift Registers (LFSRs), this requires very little hardware overhead. In this paper,
structure design and optimization of a Built-In Self-Test (BIST) design based on twodimensional
(2-D) Linear Feedback Shift Registers (LFSRs) are described. The 2-D LFSRs
can generate both precomputed test patterns (for detecting random-pattern-resistant faults)
and random patterns (for detecting random-pattern-detectable faults) and have the
advantages of high fault coverage and at-speed testing. The configurable 2-D LFSR test
generator can be adopted in two basic BIST execution options: test-per-clock (parallel BIST)
and test-per-scan (serial BIST). Generally, a circuit or system consumes more power in test
mode than in normal mode. This extra power consumption can give rise to severe hazards in
circuit. For LFSR-Reseeding Scheme takes advantage of the fact that the number of
transitions in a test cube is always less than the number of blocks that do not contain
transitions, the logic value fed into the scan chain is simply held constant. This approach
reduces the number of transitions in the scan chains and thus minimizing power consumption.
INTRODUCTION
The increasing demands for high-density and high performance integrated circuits dictate
the Built-In Self Test (BIST) schemes to guarantee high fault coverage, which is expected to
be produced by a simple test-pattern generator in an acceptable number of vectors. The BIST
involves performing the test-vector generation and the output-response analysis on a chip
through the built-in hardware. BIST is a powerful Design For-Testability (DFT) technique for
addressing highly complex Very-Large-Scale Integration (VLSI) testing problems. BIST
designs include on-chip circuitry to provide test patterns and analyze output responses.
Circuit Under Test (CUT)
Circuit under test is the circuit which is to be tested to find the faults present in that circuit.
Controllability, observability and predictability are the three most important factors that
determine the complexity of driving a test for a circuit. A circuit under test fails when its
observed behavior is different from its expectated behavior.
Output Response Analyzer (ORA)
The Output Response Analyzer (ORA) compacts the output responses of the CUT to the
many test patterns produced by the TPG into a single Pass/Fail indication. The output
response analyzer is sometimes referred to as an Output Data Compaction (ODC) circuit. The
significance of the output response analyzer is that there is no need to compare every output
response from the circuit under test with the expected output response external to the device.
Only the final Pass/Fail indication needs to be checked at the end of the BIST sequence in
order to determine the fault- free/faulty status of the CUT.
LFSR-Reseeding Scheme
Power dissipation during test is a significant problem as the size and complexity of
systems-on-chip (SOCs) continue to grow. A new test-data-compression scheme based on
linear feedback shift registers (LFSR) reseeding that significantly reduces power consumption
during test. The basic idea in LFSR reseeding is to generate deterministic test cubes by
expanding seeds. A seed is an initial state of the LFSR that is expanded by running the LFSR.
The proposed encoding scheme encodes each test cube with two kinds of data: “hold flags”
and “data bits.” Each test cube is divided into several blocks, and each block has a 1-bit hold
flag. The hold flag indicates whether a transition occurs in a block [3].
CONCLUSION
A new approach to optimize configurable 2-D LFSR for generating both embedded and
random test pattern in BIST has been proposed. This configurable 2-D LFSR-based test
pattern generator generates: 1) a deterministic sequence of test patterns for random-patternresistant
faults 2) random test patterns for random-pattern-detectable faults. The configurable
2-D LFSR test generator can be adopted in two basic BIST execution options: test-per-clock
(Parallel BIST) and test-per-scan (serial BIST). The proposed 2-D LFSR structure will be
implemented in SPARTAN-3E FPGA by using VHDL. By comparing normal LFSR and 2DLFSR,
the percentage improvement for fault coverage is 16%. The memory transition is high
in test-per-scan BIST compared to test-per-clock BIST. LFSR reseeding encoding technique
is used in test-per-scan BIST to reduce the memory transition and power consumption. This
approach reduces the number of transitions in the scan chains and thus minimizing power
consumption. By using encoding algorithm, the percentage improvement for power
consumption is 17%.