29-05-2012, 12:28 PM
A Mixed Analog-Digital Simulator for ASIC Using a Novel Block Tearing Approach
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Abstract
This paper reports a mixed-mode simulator for timing
verification of analogdigital CMOS VIS1 circuits. It was developed
by combing the SF'ICE techniques for analog circuit simulation and
the gate level techniques for digital circuit simulation based on the
event-driven method. A new scheme called Block Tearing (BT)
approach at the macrocell level is proposed for memory storage
savings while preserving reasonable accuracy. Benchmark tests of
several example circuits show good performance in terms of speed
and accuracy. The simulator is well suited for hierarchial VLSI
circuits which are cell-based such as current ASIC circuit design.
1. Introduction
In recent years, with the complexity of integrated circuits, the
rapid growth and the need for a mixed analog-digital circuit design
are becoming increasingly important. There is no doubt the
verification of these circuits using standard circuit simulators such as
SPICE2 [l] and ASTAP [2] will give accurate results. However, it
will face hazardous situations for very large circuits, i.e., it demands
huge computation time and large memory requirement. For digital
circuit simulation, simulation time can be dramatically reduced
using the timing level (e.g.. RELAX2[3]) or gate level (e.g.
MOTA[4]) simulation. The mixed mode simulator now in practical
VLSI design combines the above two simulations methods above
but with different algorithms used in their implementations.
In general, a few common characteristics of VLSI circuits can
be classified into two categories. First, most of the VLSI circuits
have highly repetitive structures such as those constructed by
macrocells [6]-[7]. Second, many mixed analog-digital circuits
actually consist of a large portion of digital circuits while a small
amount of analog circuits which are weakly coupled. As a consequence,
both digital and analog circuits can be simulated with
different simulators simultaneously. A prerequisite for using
different simulators for both types of circuits is the way to partition
the circuit. In this paper, a new partition algorithm called the Block
Tearing in both cell block decomposition and timing partition is
implemented in a newly developed mixed-mode simulator. The
simulator can executive cell block decomposition at the macrocell
level and then use different rate for each macrocell. The simulator
has been coded in C and has been tested on a number of examples
such as A/D converter, counter, register and 8-bit parallel-in-serial
-out circuits. Reasonable speed and accuracy has been achieved.
2. An Event-driven Block Tearing Approach
The key issue in designing a simulator using the so called block
tearing approach is the way to partition the circuit into subcircuit
and also can handle the multirate behavior. This block tearing
approach. which is based on the eventdriven method, decomposes a
large circuit into subcircuit (or called blocks) based on both the
analog and digital circuit nature and the analysis time. The simulator
with block tearing approach can improve the convergence and less
memory space is required than conventional circuit simulator so that
it is useful for mixed-mode circuit. Moreover, owing to its pipeline
nature, this approach can also be implemented into parallel computer
to speed up the simulation.
2. I A General Multirate Behavior
Conventional circuit simulator usually computes the solution
of each node variable at each time point by the direct method. A
number of circuit simulators have been attempted to improve the
efficiency in the conventional direct method by using different
approaches. The eventdriven methodology can improve the performance
of the circuit simulatior by exploiting the characteristics of
digital circuits. Moreover, it can be improved to exploit two
properties of waveforms called "latency" and "multirate behavior".
The general multirate behavior is based on the event-driven
methodology, and if it takes advantage of the relative inactivity of
r 1 [m] Ilxn
mxm
(a) (b)
Fig. 1 M A matrix for different scheme (a) standard sparse
matrix technique used in Spice, (b) new method.
Fig.2 Feedback loop (A2 and A3) is treated as a macrocell.
0-7803-1375-5/93$03.0Q0 1993 IEEE 527
VLSI circuits. It has several advantages: (1) Differect algorithm
can be employed in the simulator, particularly for analog-digital
mixed signal circuit (2) Memory requirement can be reduced as
shown in the comparison in Fig. 1. For conventional circuit
simulation using Sparse matrix technique. memory space of n2 ( n
is number of nodes in the network ) is required. For the new
approach, only m2 ( m is number of maximum nodes between these
macrocells in the network ) is required. where m<cn If the feedback
loop exists, each feedback loop is treated as one circuit block (e.g.,
A2 and A3) are given in Fig. 2. (3) Fast convergence speed can be
achieved since large circuit matix solution can be prevented.
In general, for a mixed-mode simulator, the time step varies
according to the types of circuits. i.e.. either analog or digital. For
transient analysis, the simulation of analog circuit needs a circuitlevel
algorithm in which dynamic time step is used, while the
digital circuit needs a gate-level algorithm in which uniform time
step is usually used. As a result. a general multirate behavior with
event-driven scheme can be used that allows the use of different step
Bizes to solve different subcircuits. In the scheme, two factors must
be considered : (1) at the input ports, because each subcircuit is
simulated with different step size. how to transfer discrete signals
changing at different rate from one subcircuit to another subcircuit 7
(2) at the output ports, every subcircuits have loading effect problem
and how to include them in the solution 7
Fig.3 (a) Connection betwan subcircuits and (b) Associated
MNA matrix for each subcircuit
The first factor refers to transform different signal rates on the
output of each subcircuit to the same signal rate. After the same
signal rate is built at the output of each subcircuit the cubic-spline
interpolation method is used for deciding the time step for the next
subcircuit during transient analysis. In general, during the
cubic-spline inteqolation over a given interval of time, the number
of time steps chosen can be increased for achieving more accurate
results. The second factor is dependent on the loading effect of each
subcircuit For example, we have a partitioned circuit as shown in
Fig3(a), in which subcircuit NO is the previous stage which has
been simulated and has n fanouts denoted by NI. Nz ..., N,. Each
subcircuit has the MNA matrix given in Fig3(b). From the
simulation results for circuit No by assuming voltage Va at the
output of NO is known, the current at the input N1 can be solved
and so are the currents for other subcircuits Nz, Nj.. N,. Ian
corresponds to the input current of subcircuit N,. The loading
impedance versus time at the output node of circuit NO can be
obtained by a t ) = v a / c I k . All of the above subcircuits are
simulated once again which need to take into account the loading
impedence versus time at the output terminal of every subcircuits.
Both cubic-spline interpolation and linear interpolation method can
also be applied for determining the loading impedance at any instant
of time. Furthermore. if an analog subcircuit is followed by a
digital subcircuit, the input capacitance at the input of the digital
circuit is considered as the load at the output of the previous analog
circuit.
2.2 Block Tearing with Pipeline Structure
As described earilier, a general multirate scheme based on the
event-driven method uses different step size to simulate different
macrocells in a circuit. Here, a novel partitioning approach called
block tearing method was proposed, in which timing partition is
used (Fig.4) in addition to the partition of subcircuits accroding
circuit types. In other words, each blocks are partitioned based on the
circuit property and time. For the time partition, a command in the
circuit description. Le.,
is used, where tstep is a time interval.
.PRINT tstep tfinal.
t = fstep
I I I I I
I I ( for digital circuit ) I I - - I
Variable time step
( for analog circuit )
W W
Fig.4 Timing putition for analog and digital circuits.
3Ti me
: executed block n: active block [7 : inactive block
Fig.5 Block Turing brad on the maaoall damnposition
i d timing partitioning.
The simulation with block tearing are similar to general
multirate scheme for earlier decomposed macrocells. Fig5 shows
the proposed block tearing approach. For example, four blocks B11,
B12, B21, B22 as shown, at the beginnimg, Bll is in active state.
After B11 is simulated, it exciting neighbor block, both 812 and
B21 are active simultaneously. Finally. B22 is actived after B12 and
B21 have been simulated. Moreover, we may simultaneously
simulate many active blocks resulting from the pipeline structure by
the parallel computer. The arrows in the figure shows the status of
the active and inactive of each block circuit during simulation.
Using the appropriate circuit partition, the present mixed-mode
528
simulator can be further implemented in multi-processor machines
to speed up since these partitioned macrocells are built upon the
pipeline structure.
3. Implementation of the Mixed-Mode Simulator
The flowchart of the simulator is shown in Fig.6. The simulator
provides an enviroment in which the designer can have much more
flexibility by entering and modifying circuit description. The
mapping is proposed which regards macrocells as black boxes. It
hansforms the arbitrary labeling nodes to a regular netlist. The
partition will decompose a large circuit into analog and digital
portions. Each digital or analog circuits are further decomposed into
subcircuits which are treated as macrocells. After the decomposition,
scheduling is necessary for the simulator. It schedules the
Input-Output port of each macrocells which use the unilateral signal
flow path if there are no feedback among these macrocells. If a
feedback loop is encountered during scheduling, we regard this
feedback loop (such as A2 and A3 in Fig.3) as a large subcircuit.
Finally. rescheduling are made until there are no feedback loops
exists. Once the macrocells are already partitioned, different
algorithms are applied to analog and digital circuits using either
circuit level or gate level simulation. The simulation algorithm for
analog circuit adopted the Spice approach while the algorithm for
digital circuits is used at the gate level. Since the mixed-mode
simulator allows the mixing of analog and digital types, it is ideally
suited for verifying hierarchial VLSI circuits design.
f LNode maprping'
macrocell Partition into macro's
decomposition t Timing
par ti tion
Loop detection
and I Rescheduling 1
c END 1
Fig. 6 Flowchw of the developed mixed-mode simulator.
4. Simulation Results and Benchmarks
Benchmark tests of several circuit examples are described as
follows. Fig.7 is a 10-stage CMOS inverter for the comparison of
simulation accuracy and memory requirement using Spice, gate level
simulator and the present mixed-mode simulator. Fig. 8 shows the
simulated output waveforms, in which the gate level simulator will
loss accuracy by comparing with that of Spice. However, the
mixed-mode simulator has the same accuracy as Spice. For the
memory requirement comparison as given in Table 1, the
third-column shows the memory storage for the example circuits by
Spice simulation and the fourthcolumn is the memory storage by
the new method. It reveals that memory storage has been greatly
reduced. The second example is an A/D converter circuit as shown
in Fig.9, with the simulated output given in Fig.10. The
simulation time on the Aparc2 machine is 162 sec. By comparing
with that of Allen et.al. [7], the simulation time of the same circuit
using the present simulator is 1:1.6 to that of [7]. Our results show
that the new mixed-mode simulator is faster than that of [7]. A third
example is a parallel-in-Serial-out (PS) circuit shown in Fig.11 with
simulation time 6912 sec and the simulated output is given in
Fig.12. This circuit consists of repetitive macrocells which can be
easily simulated using the present mixed-mode simulator while it
has difficulty to be simulated using Spice.