19-03-2012, 03:28 PM
CSCI 320 Computer Architecture Handbook on Verilog HDL
Computer Architecture -verilog-handbook.pdf (Size: 80 KB / Downloads: 24)
INTRODUCTION
Verilog HDL is a Hardware Description Language (HDL). A Hardware Description
Language is a language used to describe a digital system, for example, a computer or a component
of a computer. One may describe a digital system at several levels. For example, an HDL might
describe the layout of the wires, resistors and transistors on an Integrated Circuit (IC) chip,
i. e., the switch level. Or, it might describe the logical gates and flip flops in a digital system,
i. e., the gate level. An even higher level describes the registers and the transfers of vectors of
information between registers. This is called the Register Transfer Level (RTL). Verilog
supports all of these levels. However, this handout focuses on only the portions of Verilog which
support the RTL level.
1.1 What is Verilog?
Verilog is one of the two major Hardware Description Languages (HDL) used by hardware
designers in industry and academia. VHDL is the other one. The industry is currently split on
which is better. Many feel that Verilog is easier to learn and use than VHDL. As one hardware
designer puts it, “I hope the competition uses VHDL.” VHDL was made an IEEE Standard in
1987, and Verilog in 1995. Verilog is very C-like and liked by electrical and computer engineers
as most learn the C language in college. VHDL is very Ada-like and most engineers have no
experience with Ada.
What is VeriWell?
VeriWell is a comprehensive implementation of Verilog HDL originally developed by
Wellspring Solutions, Inc. VeriWell supports the Verilog language as specified by the OVI
language Reference Manual. VeriWell was first introduced in December, 1992, and was written to
be compatible with both the OVI standard and with Cadence’s Verilog-XL.
VeriWell is now distributed and sold by SynaptiCAD Inc. For Windows 95/NT, Windows 3.1,
Macintosh, SunOS and Linux platforms, SynaptiCAD Inc. offers FREE versions of their VeriWell
product available from http://www.syncadver_down.htm. The free versions are the same as
the industrial versions except they are restricted to a maximum of 1000 lines of HDL code.
Why Use Verilog HDL?
Digital systems are highly complex. At their most detailed level, they may consists of millions
of elements, i. e., transistors or logic gates. Therefore, for large digital systems, gate-level design
is dead. For many decades, logic schematics served as the lingua franca of logic design, but not
any more. Today, hardware complexity has grown to such a degree that a schematic with logic
gates is almost useless as it shows only a web of connectivity and not the functionality of design.
Since the 1970s, Computer engineers and electrical engineers have moved toward hardware
description languages (HDLs). The most prominent modern HDLs in industry are Verilog and
VHDL. Verilog is the top HDL used by over 10,000 designers at such hardware vendors as Sun
Microsystems, Apple Computer and Motorola. Industrial designers like Verilog. It works.