14-11-2012, 01:58 PM
A New Architecture for Signed Radix-2m Pure Array Multipliers
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Abstract
We present a new architecture for signed multiplication
which maintains the pure form of an array multiplier, exhibiting
a much lower overhead than the Booth architecture.
This architecture is extended for radix-2m encoding, which
leads to a reduction of the number of partial lines, enabling
a significant improvement in performance and power consumption.
The flexibility of our architecture allows for the
easy construction of multipliers for different values of m,
as opposed to the Booth architecture for which implementations
form > 2 are complex. The results we present show
that the proposed architecture with radix-4 compares favorably
in performance and power with the Modified Booth
multiplier. We have experimented our architecture with different
values of m and concluded that m = 4 minimizes
both delay and power.
Introduction
Multiplier modules are common to many DSP applications.
The fastest types of multipliers are parallel multipliers.
Among these, the Wallace multiplier [1] are among the
fastest. However, they suffer from a bad regularity. Hence,
when regularity, high-performance and low power are primary
concerns, Booth multipliers tend to be the primary
choice [2, 3, 4, 5, 6]. Booth multipliers allow the operation
on signed operands in 2’s-complement. They derive
from array multipliers where, for each bit in a partial product
line, an encoding scheme is used to determine if this bit
is positive, negative or zero. The Modified Booth algorithm
achieves a major performance improvement through radix-4
encoding.
Related Work
A substantial amount of research work has been put
into developing efficient architectures for multipliers given
their widespread use and complexity. Schemes such as bisection,
Baugh-Wooley and Hwang [7] propose the implementation
of a 2’s complement architecture, using repetitive
modules with uniform interconnection patterns. However,
it is not permitted an efficient VLSI realization due to the
irregular tree-array form used. The same non-regularity aspect
is observed in [8], where a scheme of a multiplexerbased
multiplier is presented. In [6] an improvement of
this technique is observed where the architecture has a more
rectangular layout than [8].
The techniques described above have been applied to
conventional array multipliers whose operation is performed
bit by bit and sometimes the regularity of the multipliers
is not preserved. More regular and suitable multiplier
designs based on the Booth recoding technique have been
proposed [2, 3, 5]. The main purpose of these designs is to
increase the performance of the circuit by the reduction of
the number of partial products. In the Modified Booth algorithm
approximately half of the partial products that need to
be added is used.
Conclusions
We have presented an array architecture multiplier that
operates on 2’s complement numbers using radix-2m encoding.
We have presented results that show significant improvement
in delay and power. The radix-2m array multiplier
has been used before in a similar manner in the wellknown
Booth architecture. However, the Booth multiplier
implies some overhead in terms of coding to handle the sign
bit. The results demonstrate that because of our simpler architecture,
2’s complement multiplication can be performed
with just two thirds the power of a radix-4 Booth multiplier.
According to our results, increasing the radix can improve
the efficiency up to a certain point. Although the good
results we have found were for m = 2 compared to Modified
Booth, we could show that the modules for m = 4
present better results with delay and power reduction improvements.
Such higher order radices are more difficult to
implement with the Booth architecture.