25-08-2014, 11:21 AM
Carry Select Adder
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Abstract
Carry Select Adder (CSLA) is one of the fastest adders used
in many data-processing processors to perform fast arithmetic functions.
From the structure of the CSLA, it is clear that there is scope for reducing
the area and power consumption in the CSLA. This work uses a simple and
efficient gate-level modification to significantly reduce the area and power
of the CSLA. Based on this modification 8-, 16-, 32-, and 64-b square-root
CSLA (SQRT CSLA) architecture have been developed and compared with
the regular SQRT CSLA architecture. The proposed design has reduced
area and power as compared with the regular SQRT CSLA with only a
slight increase in the delay. This work evaluates the performance of the
proposed designs in terms of delay, area, power, and their products by
hand with logical effort and through custom design and layout in 0.18- m
CMOS process technology. The results analysis shows that the proposed
CSLA structure is better than the regular SQRT CSLA
I. INTRODUCTION
Design of area- and power-efficient high-speed data path logic sys tems are one of the most substantial areas of research in VLSI system
design In digital adders, the speed of addition is limited by the time
required to propagate a carry through the adder. The sum for each bit
position in an elementary adder is generated sequentially only after the
previous bit pposition has been summed and a carry propagated into the
next position.
This brief is structured as follows. Section II deals with the delay
and area evaluation methodology of the basic adder blocks.
VI. CONCLUSION
In this paper, we have presented new parallel FIR filter structures,
which are beneficial to symmetric convolutions when the number of
taps is the multiple of 2 or 3
III. BEC
Fig. 3 illustrates how the basic function of the CSLA is obtained by
using the 4-bit BEC together with the mux.A structure and the function table of a 4-b BEC are shownin Fig. 2 and Table II, respectively.
Fig. 3 illustrates how the basic function of the CSLA is obtained by
using the 4-bit BEC together with the mux. One input of the 8:4 mux
gets as it input (B3, B2, B1, and B0) and another input of the mux is the
BEC output. This produces the two possible partial results in parallel
and the mux is used to select either the BEC output or the direct inputs
according to the control signal Cin. The importance of the BEC logic
stems from the large silicon area reduction when the CSLA with large
number of bits are designed.
DELAY AND AREA EVALUATION METHODOLOGY OF THE BASIC
ADDER BLOCKS
The AND, OR, and Inverter (AOI) implementation of an XOR gate is
shown in Fig.The gates between the dotted lines are performing the
operations in parallel and the numeric representation of each gate indcates the delay contributed by that gate.
IV. DELAY AND AREA EVALUATION METHODOLOGY OF REGULAR
16-B SQRT CSLA
The structure of the 16-b regular SQRT CSLA is shown in Fig. 4. It
has five groups of different size RCA. The delay and area evaluation of
each group are shown in Fig. 5, in which the numerals within [] specify
the delay values, e.g., sum2 requires 10 gate delays. The steps leading
to the evaluation are as follows.
DELAY AND AREA EVALUATION METHODOLOGY OF MODIFIED
16-B SQRT CSLA
The structure of the proposed 16-b SQRT CSLA using BEC for RCA
with to optimize the area and power is shown in Fig. 6. We
again split the structure into five groups. The delay and area estimation
of each group are shown in Fig. 7. The steps leading to the evaluation
are given here.
ASIC IMPLEMENTATION RESULTS
The design proposed in this paper has been developed using Verilog-HDL and synthesized in Cadence RTL compiler using typical libraries of TSMC 0.18 um technology.
. CONCLUSION
A simple approach is proposed in this paper to reduce the area and
power of SQRT CSLA architecture. The reduced number of gates of
this work offers the great advantage in the reduction of area and also the
total power. r. The compared results show that the modified SQRT CSLA
has a slightly larger delay (only 3.76%), but the area and power of the
64-b modified SQRT CSLA are significantly reduced by 17.4% and
15.4% respectively. The power-delay product and also the area-delay
product of the proposed design show a decrease for 16-, 32-, and 64-b
sizes which indicates the success of the method and not a mere tradeoff
of delay for power and area.