29-06-2013, 02:17 PM
A REPORT ON RING COUNTER DESIGN
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Abstract
This report illustrates design of Mod-8 Ring Counter designed using D flip-flop. They are initialized using pass transistor. The report also illustrates the layout implementation upto LVS of the Mod-8 Ring Counter. Minimum settling time and minimum area has been the main design criteria.
Introduction
A ring counter is a Shift Register (a cascade connection of flip-flops) with the output of the last flip flop connected to the input of the first. It is initialized such that only one of the flip flop output is 1 while the remainder is 0. The 1 bit is circulated so the state repeats every n clock cycles if n flip-flops are used. The "MOD" or "MODULUS" of a counter is the number of unique states. The MOD of the n flip flop ring counter is n. We are designing MOD-8 Ring counter, so we use 8 D flip-flops.
Working
We have designed MOD-8 Ring counter with asynchronous reset. The asynchronous reset has been achieved with the help of pass transistor, as shown in fig1. As we apply 0 at r for short duration (or one cycle of clock), it makes output p7high and all other outputs namely p0-p6 low. This initializes the Ring Counter with 00000001and then it sets into functioning. We can say the method to achieve reset to be novelty of our design, because we have avoided D Flip-Flop with set reset pin, thus saving 10 transistors with each D Flip-Flop and so utilizing less area. For information D Flip-Flop with set and reset has been shown in fig3 and can be seen that it requires six3-input NAND Gate while D Flip-Flop without set and reset pin requires one 3-input NAND Gate and five 2-input NAND Gate.
Application
1. The ring counter can be used to derive low distortion sine wave from a crystal controlled clock. This is accomplished by dividing the clock frequency to obtain frequency of sine wave and then filtering out the harmonics using suitable filter [1].
2. Ring counter can also be used to create a random number generator circuit. A random number generator includes a ring oscillator having an EX-OR gate and four inverters together forming a loop. This loop enters stable state for a start signal having the low level and oscillates for the start signal having the high level. When the start signal has a pulse of a width shorter than the loop's delay time, output nodes responsively, sequentially enter metastable state hovering between the high and low levels. The metastable waveform becomes smaller with time and finally disappears. As metastable state cannot be controlled in longevity, it disappears at any random number node. A counter thus outputs a signal serving as true random number data depending on the longevity of the metastable state. A random number generator miniaturized and having reduced power consumption, and of high performance can thus be implemented. [2]
Calculation of W/L
We have done calculation of W/L method with logical effort, but since it is a digital circuit and we want to minimize the area without compromising on the functionality of the circuit, so we tried to choose minimum W/L, that will do the job, thus optimizing area.
Using logical effort, the values of width calculated for the D Flip-Flop varies between 723 nm to 47 nm, but the values below 440 nm is not possible because of technology limitation, therefore, we chose for area optimization.
Conclusion
We tried to achieve lower area in our design of MOD-8 Ring counter, but later while surveying concerned literature[5], we came to know that the area would have been even reduced if we used pass transistor for implementing D Flip-Flop, instead of using NAND gates.