30-06-2012, 11:37 AM
A Reconfigurable Applcation Specific Instruction Set Processor for Viterbi and Log-MAP Decoding
A Reconfigurable Applcation Specific Instruction Set.pdf (Size: 7.7 MB / Downloads: 169)
Abstract
Future mobile and wireless communications networks
require flexible modem architectures with high performance.
This paper presents a dynamically reconfigurable
application specific instruction set processor (dr-ASIP) for the
application domain of channel coding in wireless communications
systems: FlexiTreP, It features Viterbi and Log-MAP decoding
for support of binary convolutional codes and binary as well as
duobinary turbo codes.
INTRODUCTION
Next generation mobile communication networks, beyond
3G (B3G), feature new services, especially multimedia applications,
high data rates, and multi-access interoperability. The
International Telecommunication Union expects that new radio
access technologies will be integrated with already existing
wireless and mobile networks like UMTS, WLAN and DVB
into a heterogeneous network. Seamless services with soft
handover must be guarantied for varying data rates of few
kbps up to several hundred Mbps. Modem architectures must
adapt to these diverse requirements and support different
technologies and standards at the same time. Thus flexibility
becomes a dominant aspect for future modems.
CONVOLUTIONAL CODES
In convolutional codes forward error correction is enabled
by introducing parity bits at the encoder. Figure 1 shows a
generic binary convolutional encoder. Binary convolutional
codes are characterized by a single binary input sequence
(information sequence). They are fully specified by the constraint
length K-=+ 1 with m the size of the shift register,
a feedback polynomial GI, B, and generator polynomials Gi for
the parity bits Note that one output sequence can be equal to
the input sequence: the systematic information. The number
of output values per information bit defines the rate R of the
code.
ASIP DESIGN
General Considerations
Before designing the application specific processor, general
architectural choices had to be made. The Log-MAP algorithm
is computationally more expensive than the VA and will
therefore be discussed first.
Various windowing schemes must be supported. Therefore
the recursions are programmable meaning that the window
size and acquisition length depend only on the number of
instruction executionsi and that the memory accesses are
defined by the instructions only. This gives flexibility for
instance to adjust the acquisition length to the code structure
and to the communication channel conditions. The different
recursions are processed sequentially on the same hardware,
and forward or backward recursion can be performed first. The
soft output (either A Posteriori Probability (APP) or Extrinsic
Information) is computed, in parallel with the second recursion.
One recursion step of turbo code applications is processed,
in a single cycle for high throughput support. Therefore it
must be possible to read channel values.
CONCLUSION
Application specific flexibility mandatory
flexibility and performance requirements of B3G communications
systems. It can be achieved by application specific
instruction set processors with specialized pipeline topology
and dedicated communication and memory infrastructure.
Dynamic reconfigurability is necessary to switch during run
time between different coding schemes. In this paper we
presented a dynamically reconfigurable ASIP (dr-ASIP) for
the application domain of trellis based, channel decoding.
FlexiTreP.