24-03-2012, 11:43 AM
FPGA Based Implementation of Convolutional Encoder- Viterbi
Decoder Using Multiple Booting Technique
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Introduction
Generally, there are two schemes of channel coding: one of them is the block coding
that does not require memory, and the second is Convolutional coding that requires memory.
Convolutional coding is used for the channel coding in digital communication systems,
because it facilitates a better error correction compared with the block coding although it
requires an extensive memory in decoding [1]. Viterbi algorithm is one of the Convolutional
coding algorithms that has been widely applied to decode and estimate the information in
communications and signal processing units[2].
Background Theory
2.1 Convolutional Encoder
C o nvolutional encoder consists of linear shift register and XOR gates; and is
generally characterized in (n, k, m+1) format, where: n represents the number of outputs of
the encoder; k is the number of inputs of the encoder, m is the number of memory elements
(Flip- Flops) and m+1 represents the constraint length. The rate of this encoder can be
represented as k/n. Figure (1) shows the Convolutional encoder with (2, 1, 3) format and the
generating polynomials:
Viterbi Decoder
The Viterbi decoding algorithm is a decoding process for Convolutional codes. This
algorithm is based on maximum likelihood algorithm. When the received signal is sampled
and quantized into two levels, either zero or one, the hard decision decoding will be used. In
such decoding, the path through the trellis diagram is determined using hamming distance
measure. Where the trellis represents the extension of the state diagram that explicitly
demonstrates the state diagram with the time. The hamming distance is defined as a number
of bits that are different between the observed symbol at the decoder and the sent symbol
from the encoder [8].
Multiple Booting Technique
The Spartan-3E Starter Kit board [9] supports a variety of FPGA configuration
options. One of these options is programming the on-board 128Mbit Intel Strata Flash
(parallel NOR Flash PROM), then configuring the FPGA from the image stored in this Flash
PROM using BPI Up or BPI Down configuration modes. Moreover, an FPGA can be
dynamically loaded with two different FPGA configurations using the Spartan-3E FPGA’s
Multi Boot mode. Figure (5) demonstrates the Multiple Booting Technique for two different
applications.