19-11-2012, 05:04 PM
A SEMINAR REPORT ON CLOCKLESS CHIPS
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ABSTRACT
Clockless chips are electronic chips that are not using clock for timing
signal. They are implemented in asynchronous circuits. An asynchronous circuit
is a circuit in which the parts are largely autonomous. They are not governed by
a clock circuit or global clock signal, but instead need only wait for the signals
that indicate completion of instructions and operations. These signals are
specified by simple data transfer protocols. This digital logic design is
contrasted with a synchronous circuit which operates according to clock timing
signals.
The term asynchronous logic is used to describe a variety of design styles,
which use different assumptions about circuit properties. These vary from the
bundled delay model - which uses ’conventional’ data processing elements with
completion indicated by a locally generated delay model - to delay-insensitive
design - where arbitrary delays through circuit elements can be accommodated.
The latter style tends to yield circuits which are larger and slower than
synchronous (or bundled data) implementations, but which are insensitive to
layout and parametric variations and are thus "correct by design."
INTRODUCTION
DEFINITION
Every action of the computer takes place in tiny steps, each a billionth of
a second long. A simple transfer of data may take only one step; complex
calculations may take many steps. All operations, however, must begin and end
according to the clock’s timing signals.
The use of a central clock also creates problems. As speeds have increased,
distributing the timing signals has become more and more difficult. Present-day
transistors can process data so quickly that they can accomplish several steps in
the time that it takes a wire to carry a signal from one side of the chip to the
other. Keeping the rhythm identical in all parts of a large chip requires careful
design and a great deal of electrical power. Wouldn’t it be nice to have an
alternative?
Clockless approach, which uses a technique known as asynchronous logic,
differs from conventional computer circuit design in that the switching on and
off of digital circuits is controlled individually by specific pieces of data rather
than by a tyrannical clock that forces all of the millions of the circuits on a chip
to march in unison. It overcomes all the disadvantages of a clocked circuit such
as slow speed, high power consumption, high electromagnetic noise etc.
CLOCK CONCEPT
The clock is a tiny crystal oscillator that resides in the heart of every
microprocessor chip. The clock is what which sets the basic rhythm used
throughout the machine. The clock orchestrates the synchronous dance of
electrons that course through the hundreds of millions of wires and transistors of
a modern computer.
Such crystals which tick up to 2 billion times each second in the fastest of
today’s desktop personal computers, dictate the timing of every circuit in every
one of the chips that add, subtract, divide, multiply and move the ones and zeros
that are the basic stuff of the information age.
CLOCK LIMITATIONS
There are problems that go along with the clock, however.
Clock speeds are now in the gigahertz range and there is not much room for
speedup before physical realities start to complicate things. With a gigahertz
clock powering a chip, signals barely have enough time to make it across the
chip before the next clock tick. At this point, speedup up the clock frequency
could become disastrous. This is when a chip that is not constricted by clock
speeds could become very valuable.
ASYNCRONOUS VIEW
By throwing out the clock, chip makers will be able to escape from huge
power dissipation. Clockless chips draw power only when there is useful work
to do, enabling a huge savings in battery-driven devices.
Like a team of horses that can only run as fast as its slowest member, a
clocked chip can run no faster than its most slothful piece of logic; the answer
isn’t guaranteed until every part completes its work. By contrast, the transistors
on an asynchronous chip can swap information independently, without needing
to wait for everything else. The result? Instead of the entire chip running at the
speed of its slowest components, it can run at the average speed of all
components. At both Intel and Sun, this approach has led to prototype chips that
run two to three times faster than comparable products using conventional
circuitry.
Another advantage of clockless chips is that they give off very low levels of
electromagnetic noise. The faster the clock, the more difficult it is to prevent a
device from interfering with other devices; dispensing with the clock all but
eliminates this problem. The combination of low noise and low power
consumption makes asynchronous chips a natural choice for mobile devices.
PROBLEMS WITH SYNCRONOUS CIRCUITS
Synchronous circuits are digital circuits in which parts are synchronized
by clock signals.
In an ideal synchronous circuit, every change in the logical levels of its
storage components is simultaneous. These transitions follow the level change
of a special signal called the clock signal. Ideally, the input to each storage
element has reached its final value before the next clock occurs, so the behavior
of the whole circuit can be predicted exactly. Practically, some delay is required
for each logical operation, resulting in a maximum speed at which each
synchronous system can run.
LOW SPEED
A traditional CPU cannot "go faster" than the expected worst-case
performance of the slowest stage/instruction/component. When an asynchronous
CPU completes an operation more quickly than anticipated, the next stage can
immediately begin processing the results, rather than waiting for
synchronization with a central clock. An operation might finish faster than
normal because of attributes of the data being processed (e.g., multiplication can
be very fast when multiplying by 0 or 1, even when running code produced by a
brain-dead compiler), or because of the presence of a higher voltage or bus
speed setting, or a lower ambient temperature, than ’normal’ or expected.
HIGH POWER DISSIPATION
As we know that clock is a tiny crystal oscillator that keeps vibrating
during all time as long as the system is power on, this lead into high power
dissipation by the synchronous circuit since they use central clock in their
timings. The clock itself consumes about 30 percent of the total power supplied
to the circuit and sometimes can even reach high value such as 70 percent. Even
if the synchronous system is not active at the moment still its clock will be
oscillating and consumes power that is dissipated as heat energy. This makes
synchronous system more power consumer and hence not suitable for use in
design of mobile devices and battery driven devices.
HIGH ELECTROMAGNETIC NOISE
Since clock itself is crystal oscillator it is then associated with
electromagnetic waves. These waves produce electromagnetic noise due to
oscillations. Noise will also be accompanied by emission spectra. The higher the
speed of clock is the higher number of oscillations per second and this leak high
value of electromagnetic noise and spectra emission. This is not a good sign for
design of mobile devices too.
Apart from the problems above, the clock is synchronous circuit and globally
distributed over the components which are obviously in running in different
speed and hence the order of arrive of the timing signal is not important. Data
can be received and transmitted in any form of order regardless of there
sequential order they arrive at the fist stage of execution.
The designing of clock frequency should be so sophisticated since the
frequency of the clock is fixed and poor march of design can result problem in
the reusability of resources and interfacing with mixed-time environment
devices.