01-08-2013, 12:25 PM
Practical Phase-Locked Loop Design
Practical Phase-Locked.ppt (Size: 860 KB / Downloads: 82)
What is a PLL?
A PLL is a negative feedback system where an oscillator-generated signal is phase and frequency locked to a reference signal.
Analogous to a car’s “cruise control”
How are PLL’s Used?
Frequency Synthesis (e.g. generating a 1 GHz clock from a 100 MHz reference)
Skew Cancellation (e.g. phase-aligning an internal clock to the IO clock) (May use a DLL instead)
Extracting a clock from a random data stream (e.g. serial-link receiver)
Frequency Synthesis is the focus of this tutorial.
Charge-Pump PLL Building Blocks
Phase-Frequency Detector (PFD)
Charge-Pump (CP)
Low-Pass Filter (LPF)
Voltage-Controlled Oscillator (VCO)
VCO Level-Shifter (LS)
Feedback Divider (FBDIV)
Power Supply regulator/filter (VREG)?
Components in a Nutshell
PFD: outputs digital pulse whose width is proportional to phase error
CP: converts digital error pulse to analog error current
LPF: integrates (and low-pass filters) error current to generate VCO control voltage
VCO: low-swing oscillator with frequency proportional to control voltage
LS: amplifies VCO levels to full-swing
DIV: divides VCO clock to generate FBCLK clock
Is My PLL Stable?
PLL is 2nd-order system similar to mass-spring-dashpot or RLC circuit.
PLL may be stable or unstable depending on phase margin (or damping factor).
Phase margin is determined from linear model of PLL in frequency-domain.
Find phase margin/damping using MATLAB, loop equations, or simulations.
Stability affects phase error, settling, jitter.
Avoiding the Dead-Zone
“Dead-zone” occurs when the loop doesn’t respond to small phase errors - e.g. 10 pS phase error at PFD inputs:
PFD cannot generate 10 pS wide GoFaster and GoSlower pulses
Charge-pump switches cannot turn on and off in 10 pS
Solution: delay reset to guarantee min. pulse width (typically > 150 pS)
Voltage Regulator
Bandgap reference generates a voltage reference (~1.2V) that is independent of PVT
relies on parasitic diodes (vertical PNP)
Regulator output stage may be source-follower (NFET) or common-source amp (PFET)
source-follower requires more headroom (and area?) but is more stable
common-source amp may be unstable without Miller capacitor or other compensation
Beware of large, fast current spikes in PLL load (i.e. when changing PLL frequency range)