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ABSTRACT
A novel switched-capacitor inverter is proposed. The proposed inverter outputs larger voltage than the input voltage by switching the capacitors in series and in parallel. The maximum output voltage is determined by the number of the capacitors. The proposed inverter, which does not need any inductors, can be smaller than a conventional two-stage unit which consists of a boost converter and an inverter bridge. Its output harmonics are reduced compared to a conventional voltage source single phase full bridge inverter. In this paper, the circuit configuration, the theoretical operation, the simulation results with MATLAB/ SIMULINK, and the experimental results are shown. The experimental results accorded with the theoretical calculation and the simulation results.
KEYWORDS
1. Charge pump
2. Multicarrier PWM
3. Multilevel Inverter
4. Switched capacitor (SC)
I. INTRODUCTION
Recently, electrical energy systems, electric vehicles (EVs), and dispersed generation (DG) systems, etc., are focused because of the global environmental issues. The power electronics, converters and inverters, is a key technology in these systems [1]–[6]. The EVs and the grid connected DG systems need an inverter to convert dc to ac. Boost converters or transformers are widely used in these systems when the input voltage is smaller than the output voltage. However, a transformer or an inductor in the boost converter makes the system large, because the transformer and the inductor must have large and heavy magnetic cores to sustain the high power [5]. As a provision against the issue, a charge pump, which does not have any inductors, is applied to such systems [7]. A charge pump outputs a larger voltage than the input voltage with switched capacitors [7], [8]. When the several capacitors and the input voltage sources are connected in parallel, the capacitors are charged. When the several capacitors and the input voltage sources are connected in series, the capacitors are discharged. The charge pump outputs the sum of the voltages of the capacitors and the input voltage sources. However, a charge pump has many switching devices which make the system more complicated. A switched-capacitor (SC) inverter outputs multilevel voltages with switched capacitors [9], [10]. An SC inverter is similar to a charge pump in the topology. The SC inverter
outputs a larger voltage than the input voltage in similar way to the charge pump. However, the SC inverter also has many switching devices which make the system complicated. On the other hand, a Marx inverter, which has less switching devices compared to the SC inverter, was proposed [11]. Marx inverter can be regarded as one of the SC inverters because of its operation principle. In this paper, an SC inverter whose structure is simpler than the conventional SC inverter is proposed. It consists of a Marx inverter structure and an H-bridge. The proposed inverter can output larger voltage than the input voltage by switching the capacitors in series and in parallel. The proposed inverter does not have any inductors which make the system large. The
output harmonics of the proposed inverter are reduced by the multilevel output. In Section II, the circuit topology is introduced and the driving method is explained. In Section III, the determination method of the capacitance is described. In Section IV, losses in the proposed inverter are calculated and estimated. In Sections V and VI, simulation results with MATLAB/ SIMULINK and the results of the circuit experiments are shown.
II. CIRCUIT DESCRIPTION
Fig. 1 shows a circuit topology of the proposed inverter, where Sak, Sbk, Sck(k = 1, 2, . . . , 2n − 2) are the switching devices which switch the capacitors Ck(k = 1, 2, . . . , 2n − 1) in series and in parallel. Switches S1 − S4 are in the inverter bridge. A voltage source Vin is the input voltage source. A lowpass filter is composed of an inductor L and a capacitor C.
DETERMINATION OF CAPACITANCE
The capacitance Ck can be determined properly with considering the voltage ripple of the capacitors Ck. The smaller voltage ripple of these capacitors leads to the higher efficiency. In this section, the capacitance Ck are calculated when the maximum voltage ripple is supposed to be 10% of the maximum voltages of the capacitors. The capacitors Ck are charged when they are connected in parallel and are discharged when they are connected in series. From Fig. 3, the switches Sa1 and Sa2 of the proposed inverter (n = 2) are symmetrically driven during the half cycle of the reference waveform. Therefore, the voltage ripple of the capacitor C1 is focused.
Assuming that the power factor of the output load cos φ = 1, the longest discharging term of the capacitor C1 in the proposed inverter (n = 2) is between t2 and t3 in Fig. 3. Assuming the modulation index M = 3, the time t1, t2 and t3 in Fig. 3 are
(4)
(5)
(6)
where fref is the frequency of the reference waveform. Therefore, the maximum discharge amount Q1 of the capacitor
(7)
where Ibus is the amplitude of the bus current waveform and φ is the phase difference between the bus voltage waveform vbus and the bus current waveform ibus. Q1 supposes to be less than 10% of the maximum charge of C1. Therefore, the capacitance C1 must satisfy
(8)
When the capacitors Ck satisfy (8), the other voltage ripple which is caused by PWM is less than 10%. The peak current of the capacitor IC1 is calculated by
(9)
where rc1 is the equivalent series resistance (ESR) of the capacitor C1 and ron is the internal resistance of the switching devices. From (9), the peak current of the capacitor C1 is determined by the difference between the input voltage Vin and the voltage of the capacitor VC1, and the internal resistance of the switching devices. The difference of the voltages Vin − VC1 is small
CALCULATION OF LOSSES
In this section, the power losses of the proposed inverter (n = 2) are calculated. In the calculation, the following losses are considered:
• switching losses;
• conduction losses of the switches;
• conduction loss of the output filter;
• conduction losses and losses caused by the voltage ripple of the capacitors Ck.
These losses are calculated about the proposed inverter (n = 2).
A. Switching Losses
In this section, switching losses are calculated from the charge and the discharge of the parasitic capacitance [20]. From Fig. 3, the switches S1 and S2 are switched ON/OFF at the carrier frequency f when the reference waveform es satisfies
(13)
Therefore, the switches S1 and S2 are switched ON/OFF when the time t satisfies 0 < t < t1 or t4 < t < t5 in Fig. 3. When the reference waveform es does not satisfy (13), the switches S1 and S2 are maintained ON or OFF. Therefore, when the carrier waveforms and the reference waveform are not synchronous waveforms, the average number of switching transitions N_S1and N_S2 in one period of reference waveform is calculated as
(14)
where f is the switching frequency. When the carrier waveforms and the reference waveform are synchronous waveforms, the number of switching transitions is the maximum even number less than NS1 or NS1 + 4. The number of switching transitions is variable depending on the frequency modulation ratio f/fref . Therefore, when the synchronous waveforms are used in this modulation, the individual analysis is needed in each frequency modulation ratio. In this paper, the switching losses are calculated with the average number of switching transitions NSk, because the high switching frequency f is assumed.
For one second, this switching terms repeat fref times. Therefore, the switches S1 and S2 are switched NS1fref times and NS2fref times in one second, respectively. The same argument can be applied to the switches S3 and S4. The energy loss Eloss as the following equation occurs in one switching [20]
(15)
where Cs is the parasitic capacitance of the switching devices. Therefore, the switching losses of these switches PSk (k = 1, 2, 3, 4) are given as
(16)
The switches Sak, Sbk, and Sck (k = 1, 2) are operated alternately in each cycle of the reference waveform. Therefore, the switching losses of these switches can be calculated with considering the half cycle of the reference waveform. If the voltage ripple of the capacitors Ck is ignored, i.e., the voltage of the capacitors VCk = Vin is assumed, the switching losses of the switches Sak, Sbk, and Sck (k = 1, 2) are calculated as the following equations by the same calculation method to the (16)
(17)
(18)
All switching devices are switched when the voltage of each device is Vin. Therefore, the switching losses of the proposed inverter are smaller than the conventional voltage source full bridge inverter.
B. Conduction Losses of the Switches
There are three states on the proposed inverter (n = 2) as shown in Fig. 2; the state when all capacitors are connected in parallel, the state when one of the capacitors is connected in series, and the state when all capacitors are connected in series. However, it is obvious that the bus current ibus flows in 4 switches on each state from Fig. 2. Therefore, the total conduction loss Psr of the switches is calculated by
(19)
where ron is the internal resistance of the switching devices. On the other hand, the current flows in 6 switches in the conventional 7-level CHB inverter because the current flows in 2 switches in each H-bridge. Therefore, the total conduction loss of the switches in the conventional 7-level CHB inverter PCHB is calculated as
(20)
From (19) and (20), it is obvious that the conduction losses of the proposed inverter are less than the conventional 7-level CHB inverter when the same switching devices are used.
C. Conduction Loss of the Output Filter
The conduction losses of the filter inductance Pl and the filter capacitance Pc are calculated as the following equations:
(21)
(22)
In (21), rl is the ESR of the filter inductance L. In (22), rc and ic are the ESR and the current of the filter capacitance C.
D. Losses of the Capacitors Ck
When the capacitors Ck(k _= 2) are connected in parallel, the losses occur by the difference between the input voltage Vin and the voltages of the capacitors VCk. The voltage ripple of the capacitors ΔVk is calculated by
(23)
where iCk is the current of the capacitor Ck and t2, t3 are the time when the capacitors Ck are connected in series as shown in Fig. 3. Therefore, the losses Prip by this voltage ripple are calculated as the following equation.
SIMULATION RESULTS
Simulation was performed under the two conditions. One was for a low power inverter under the same condition with the circuit experiments. The other one was for a high power inverter. The low power inverter simulation was performed with MATLAB/SIMULINK ver. R2009a under the following conditions. The MOSFET models whose internal resistance Ron = 0.54 [Ω] and the snubber resistance Rs = 105 [Ω] were used as the switching devices. The input voltage Vin = 8.00 [V], the output resistance R = 50.0 [Ω], a filter capacitance C, and a filter inductance L were C = 0.450 [μF] and L = 1.13 [mH], the modulation index M = 3.00, the switching frequency f = 40.0 [kHz], and the reference waveform frequency fref = 1.00 [kHz]. From (8), the capacitance C1 and C3 are calculated to C1 = C3 = 143 [μF], which have ESRs rc1 = rc3 = 800 [mΩ]. Fig. 5 shows the simulated voltage waveforms of the proposed inverter (n = 2) designed for low power at 5.76 [W]. The voltages of the capacitors VCk are changed between 6.73 [V] and 7.51 [V]. Therefore, the voltage of the step in the bus voltage waveform decreases to about 90% as shown at t = 8.11 - to 8.40 [ms] in Fig. 5(a). It is caused by the 10% voltage drop at the capacitors Ck. This is accorded with the theoretical calculation. The theoretical amplitude of the output waveform is
(26)
From Fig. 5(b) and (26), it is confirmed that the amplitude of the output waveform in the simulation is smaller than the theoretical amplitude. It is also caused by the voltage reduction of the capacitors Ck. The high power inverter simulation was performed under the following conditions. The IGBT/Diode models whose internal resistance Ron = 65.0 [mΩ] and the snubber resistance Rs = 105 [Ω] were used as the switching devices. Vin = 100 [V], R = 10.0 [Ω], C = 2.25 [μF], L = 225 [μH], M = 3.00, f = 40.0 [kHz] and fref = 1.00 [kHz]. From (8), C1 and C3 are calculated to C1 = C3 = 712 [μF]. These capacitors ESRs rc1 and rc3 are 100 [mΩ]. Fig. 6 shows the simulated voltage waveforms of the proposed inverter (n = 2) designed for high power at 4.50 [kW]. The voltages of the capacitors VCk are changed between 87.0 [V] and 97.2 [V]. Therefore, the voltage of the step in the bus voltage waveform decreases to about 90% as shown
at t = 8.11 - to 8.40 [ms] in Fig. 6(a), which is the same to the simulation result in low power models. The theoretical amplitude of the output waveform is
(27)
From Fig. 6(b) and (27), it is confirmed that the amplitude of the output waveform in the simulation is smaller than the theoretical amplitude. As the result of the simulation in low power
models, the voltage reduction of the capacitors Ck appears on the bus voltage waveform. Fig. 7 shows the simulated current waveforms of the capacitor C1 in the proposed inverter (n = 2). From the (9) and the voltage of the capacitor C1, the absolute value of the peak current of the capacitor C1 under the conditions of the low power and the high power simulations are 0.676 [A]
and 56.5 [A], respectively. On the other hand, the absolute values of the peak currents in the simulation results are 0.605 [A] and 52.3 [A], respectively. The differences between the theoretical currents and the simulation results are caused by the nonlinear characteristic of the switching device models in MATLAB/SIMULINK. Fig. 8 shows the simulated spectra of the bus voltage waveform, which are normalized with the fundamental component.