15-02-2013, 02:57 PM
A Three-Dimensional Integrated Circuit(3D IC)
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INTRODUCTION
A three-dimensional integrated circuit(3D IC) is a chip in which two or more layers of active electronic components are integrated both vertically and horizontally into a single circuit.3D packaging saves space by stacking separate chips in a single package. this packaging, known as system in package(sip) or chip stack MCM. the chips in the package communicate using off-chip signaling, much as if they were mounted in separate packages on a normal circuit board.
Notable 3D Chips in 2004,Intel presented a 3D version of the pentium4 CPU. the chip was manufactured with two dies using face-to-face stacking, which allowed a dense via structure. Backside TSV are used for IO and power supply. For the 3D floorplan, designers manually arranged functional blocks in each die aiming for power reduction and performance improvement. Splitting large and high-power blocks and careful rearrangement allowed to limit thermal hotspots.
The 3D design provides 15% performance improvement(due to eliminated pipeline stages) and 15%power saving(due to eliminated repeaters and reduced wiring) compared to the 2D pentium 4. the Teraflops Research chip introduced in 2006 by Intel is an experimental 80-core design with stack memory.due to the high demand for memory bandwidth, a traditional IO approach would consume 10 to 25W.To improve upon that' Intel designers implemented a TSV based memory bus.An academic implementation of a 3D processor was presented in 2008at the university of Rochester by professor Eby Friedman and his students. The chip runs at 1.4GHz and it was designed for optimized vertical processing between the stacked chips which gives the 3D processor abilities that the traditional one layered chip could not reach. one challenge in manufacturing of the three-dimensional chip was to make all of the layers work in harmony without any obtstacles that would interface with a piece of information traveling from one layer to another.
MANUFACTURING TECHNOLOGIES
There are four ways to build a 3D IC:
Monolithic: Electronic components are built on two or more semiconductor wafers, which wafer, which is then diced into 3D ICS. There is only one substrate, hence no need for aligning, thinning, bonding. A recent breakthrough overcome the process temperature limitation by partitioning the transistor fabrication to two phase. A high temperature phase which is done before layer transfer follow by a layer transfer use ion-cut, also known as layer transfer that has been the dominant method to produce SOI wafers for the past two decades. This monolithic 3D-IC technology has been researched at Stanford university under a DARPA sponsored grant.
Wafer-on-wafer: Electronic components are built on two or more semiconductor wafers, which are then aligned, bonded, and diced into 3D ICs. Each wafer may be thinned before or after bonding. vertical connections are either built into the wafers before bonding or else created in the stack after bonding. These “through-silicin vias ”(TSVs) pass through the silicon substrates between active layers or between active layers and External bond pad. Wafer-on-wafer bonding can reduce yields, since if any 1 of N chips in a 3D IC are defective, the entire 3D IC will be defective. Moreover, the wafers must the small size.
DESIGN STYLES
Depending upon the portioning granularity, different styles can be distinguished. Gate-level integration faces multiple challenges and currently appears less practical than block-level integration.
Gate-level integration: This style partitions standard cells between multiple dies. It promises wirelength reduction and great flexibility. However, wirelength reduction may be undermined unless modules of certain minimal size are preserved. on the other hand, its adverse effects include the massive number of necessary TSV for interconnects. The design style requires 3D place-and-route tools, which are unavailable yet. Also, partitioning a design blocks across multiple dies implies that it cannot be fully tested before die stacking. After die stacking(post-bond testing), a single failed die can render several good dies unusable, undermining yield. This style also amplifies the impact of process variation, especially inter-die-variation. In fact, a 3D layout may yield more poorly than the same circuit laid out in 2D, contrary to the orginal promise of 3D IC integration.
CONCLUSION
• 3D IC design is a relief to interconnect driven IC design.
• Still many manufacturing and technological difficulties
• Needs strong EDA applications for automated design