28-02-2013, 04:44 PM
A single master I2C tutorial
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Multi Master
Multi master operation is a more complex use of I2C that lets you have
different controlling devices on the same bus. You only need to use this
mode if you have more than one microcontroller on the bus (and you want
either of them to be the bus master).
Multi master operation involves arbitration of the bus (where a master has to
fight to get control of the bus) and clock synchronisation (each may a use a
different clock e.g. because of separate crystal clocks for each micro).
Note: Multi master is not covered in this I2C tutorial as the more common
use of I2C is to use a single bus master to control peripheral devices e.g.
serial memory, ADC, RTC etc.
Data and Clock
The I2C interface uses two bi-directional lines meaning that any device
could drive either line. In a single master system the master device drives
the clock most of the time - the master is in charge of the clock but slaves
can influence it to slow it down (See Slow Peripherals below).
The two wires must be driven as open collector/drain outputs and must be
pulled high using one resistor each - this implements a 'wired AND function' -
any device pulling the wire low causes all devices to see a low logic value -
for high logic value all devices must stop driving the wire.
Note : If you use I2C you can not put any other (non I2C) devices on the
bus as both lines are used as clock at some point (generation of START and
STOP bits toggles the data line). So you can not do something clever such
as keeping the clock line inactive and use the data line as a button press
detector (to save pins).
Speed
Standard clock speeds are 100kHz and 10kHz but the standard lets you use
clock speeds from zero to 100kHz and a fast mode is also available (400kHz
- Fast-mode). An even higher speed (3.4MHz - High-speed mode) for more
demanding applications - The mid range PIC won't be up this mode yet!
Note that the low-speed mode has been omitted (10kHz) as the standard
now specifies the basic system operating from 0 to 100kHz.
Slow peripherals
A slow slave device may need to stop the bus while it gathers data or
services an interrupt etc. It can do this while holding the clock line (SCL)
low forcing the master into the wait state. The master must then wait until
SCL is released before proceeding.
Device addresses
Each device you use on the I2C bus must have a unique address. For some
devices e.g. serial memory you can set the lower address bits using input
pins on the device others have a fixed internal address setting e.g. a real
time clock DS1307. You can put several memory devices on the same IC bus
by using a different address for each.
Note: The maximum number of devices is limited by the number of
available addresses and by the total bus capacitance (maximum 400pF).
General call
The general call address is a reserved address which when output by the
bus master should address all devices which should respond with an
acknowledge.Its value is 0000000 (7 bits) and written by the master
0000000W. If a device does not need data from the general call it does not
need to respond to it.