21-06-2013, 03:26 PM
AN EFFICIENT CSLA ARCHITECTURE FOR VLSI HARDWARE IMPLEMENTATION
AN EFFICIENT CSLA.pdf (Size: 496.22 KB / Downloads: 85)
Abstract:
Carry select adder (CSLA) is known to be the fastest adder among the conventional adder structures. Due to the rapidly growing mobile industry not only the faster arithmetic unit but also less area and low power arithmetic units are needed. The modified CSLA architecture has developed using Binary to Excess-1 converter (BEC). This paper proposes an efficient method which replaces the BEC using D latch. Experimental results are compared and the result analysis shows that the proposed architecture achieves the three folded advantages in terms of area, delay and power.
INTRODUCTION:
Area and power have major role in the designing of integrated circuit because of the increase in popularity of portable systems as well as the rapid growth of power density in VLSI circuits. Addition usually influences strongly on the overall performance of digital systems and a crucial arithmetic function. Adders are most widely used in electronic applications. For example, in microprocessors, millions of instructions per second are performed. Due to the increase in the portability of the devices like mobile, laptop etc. require more battery backup. Low power and area efficient addition and multiplication have always been a fundamental requirement of high performance processors and systems. Designing efficient adder is the most difficult problem for researchers in VLSI design.
The carry-select adder (CSLA) provides a compromise between small area but longer delay ripple carry adder (RCA) and larger area with shorter delay carry look-ahead adder [6]. CSLA uses multiple pairs of ripple carry adder (RCA) to generate partial sum and carry by considering carry input Cin=0 and Cin=1, then the final sum and carry are selected by multiplexers (mux) [3].
The modified CSLA using BEC [2, 4, 6] has reduced area and power consumption with slight increase in delay. The basic idea of the proposed architecture is that which replaces the BEC by D latch with enable signal. The proposed architecture reduces the area, delay and power.
This paper is organized as follows; section III presents the detailed structure and the function of the binary to excess-1 converter logic. Section IV and section V explains the regular and modified CSLA respectively. Section VI deals with the proposed architecture. Results are analyzed in the section VII. Section VIII concludes.
REGULAR CSLA ARCHITECTURE:
As said above CSLA compromise between ripple carry adder and carry look ahead adder. The main disadvantage of regular CSLA is the large area due to the multiple pairs of ripple carry adder. The Fig. 2 shows [1] the regular 16-bit carry select adder. It is divided into five groups with different bit size RCA. From the structure of CSLA, it is evident that there is scope for reducing area and power consumption.
RESULT ANALYSIS:
The 8-bit CSLA is done by the same structure of 16-bit CSLA except group 4 and group 5. The 8th bit inputs are directly given to the full adder to complete the 8-bit sum and carry. The 32-bit CSLA is done by cascading two 16-bit CSLA and 64-bit CSLA is done by cascading two 32-bit CSLA. Table II exhibits the delay, area and power of regular, modified and proposed CSLA Simulation is carried out using Xilinx simulation tool and Spartan 2E as the target device. The major disadvantage of modified CSLA using BEC is the increasing delay. This disadvantage is overcome in proposed architecture which reduces the delay, area and power than the regular and modified CSLA.
CONCLUSION:
A regular CSLA uses two copies of the carry evaluation blocks, one with block carry input is zero and other one with block carry input is one. Regular CSLA suffers from the disadvantage of occupying more chip area. The modified CSLA reduces the area and power when compared to regular CSLA with increase in delay by the use of Binary to Excess-1 converter. This paper proposes a scheme which reduces the delay, area and power than regular and modified CSLA by the use of D-latches