22-12-2012, 03:15 PM
ANUDEEP
~146164-AnudeepECEVLSIfrontendResume.doc (Size: 162 bytes / Downloads: 14)
Career Objective:
To be lucrative to the organization and concurrently to find career growth by the virtues of
hard work and dedication.
Summary :-
Well Trained Engineer with hands on experience in VLSI front end design(6 months) and excellent academic record. Committed to the highest levels of professionalism and excellent interpersonal skills. Demonstrated expertise in Verilog HDL and ASIC design with hands on experience in Cadence tools Certified ASIC flow in IIVDT(Bangalore) with industry standard project work Seeking a challenging role in ASIC design.
Skills:
C,HDL Coding, Verilog
Logic Design
Finite State Machine
CadenceTool Suite
RTL Complier
NCVERILOG
FPGA Linux , C++
Simvision
APB Protocol
System Verilog
Project Experience:
Major Project – Advanced Diploma in VLSI Design
I2C MASTER/SLAVE CONTROLLER WITH APB INTERFACE
I2C master/slave controller is an interface that interconnects an advanced peripheral bus(APB) with Inter Integrated circuit (I2C) bus.
The APB - I2C Bridge interfaces to the APB bus on the system side and the I2C bus
Verilog Coding and simulation using Cadence NCVERILOG tool
Test bench implemented in Verilog
Synthesis using RTL Complier on TSMC 45nm technology
Mini Projects – Advanced Diploma in VLSI Design
Sequential Multiplier Design :-The sequential multiplication process will be done by shift and add the multiplier is partitioned into its data and control parts,each parts will be designed separately.the project is the design of 2 bit sequential multiplier 8 –bit A and B inputs with a result of 16 bit result
Traffic Light Controller Design:- The purpose is to design and implement a traffic light controller for a single intersection .The controller is constructed from a finite state machine used to control the actual operation of the traffic lights. We are using Verilog HDL language provides a programming language interface through which the internals of a design can be accessed during simulation including the control of a simulation run
Synchronous FIFO: FIFO is a First-In-First-Out memory queue with control logic that manages the read and write operations, generates status flags, and provides optional handshake signals for interfacing with the user logic.