05-02-2013, 02:13 PM
ARM Processor Architecture
ARM Processor Architecture.pdf (Size: 1.52 MB / Downloads: 402)
ARM Processor Cores (1/4)
ARM processor core + cache + MMU
→ ARM CPU cores
ARM6 → ARM7
– 3-stage pipeline
– Keep its instructions and data in the same memory system
– Thumb 16-bit compressed instruction set
– On-chip Debug support, enabling the processor to halt in
response to a debug request
– Enhanced Multiplier, 64-bit result
– Embedded ICE hardware, give on-chip breakpoint and
watchpoint support
ARM Architecture Version
– First ARM processor designed by ARM Limited (1990)
– ARM6 (macro cell)
ARM60 (stand-alone processor)
ARM600 (an integrated CPU with on-chip cache, MMU, write
buffer)
ARM610 (used in Apple Newton)
– 32-bit addressing, separate CPSR and SPSRs
– Add the undefined and abort modes to allow coprocessor
emulation and virtual memory support in supervisor mode
qVersion 3M
– Introduce the signed and unsigned multiply and multiplyaccumulate
instructions that generate the full 64-bit result
3-Stage Pipeline ARM Organization
Register Bank
– 2 read ports, 1 write ports, access
any register
– 1 additional read port, 1 additional
write port for r15 (PC)
Barrel Shifter
– Shift or rotate the operand by any
number of bits
ALU
Address register and
incrementer
Data Registers
– Hold data passing to and from
memory
Instruction Decoder and
Control
3-Stage Pipeline (2/2)
At any time slice, 3 different instructions may
occupy each of these stages, so the hardware in
each stage has to be capable of independent
operations
When the processor is executing data processing
instructions , the latency = 3 cycles and the
throughput = 1 instruction/cycle
Multi-Cycle Instruction
Memory access (fetch, data transfer) in every cycle
Datapath used in every cycle (execute, address calculation,
data transfer)
Decode logic generates the control signals for the data path
use in next cycle (decode, address calculation)