21-06-2014, 02:00 PM
ARM7 Data Sheet
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Introduction
The ARM7 is part of the Advanced RISC Machines (ARM) family of general purpose 32-bit
microprocessors, which offer very low power consumption and price for high performance devices. The
architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and
related decode mechanism are much simpler in comparison with microprogrammed Complex Instruction
Set Computers. This results in a high instruction throughput and impressive real-time interrupt response
from a small and cost-effective chip.
The instruction set comprises eleven basic instruction types:
• Two of these make use of the on-chip arithmetic logic unit, barrel shifter and multiplier to perform
high-speed operations on the data in a bank of 31 registers, each 32 bits wide;
• Three classes of instruction control data transfer between memory and the registers, one optimised
for flexibility of addressing, another for rapid context switching and the third for swapping data;
• Three instructions control the flow and privilege level of execution; and
• Three types are dedicated to the control of external coprocessors which allow the functionality of
the instruction set to be extended off-chip in an open and uniform way.
The ARM instruction set is a good target for compilers of many different high-level languages. Where
required for critical code segments, assembly code programming is also straightforward, unlike some RISC
processors which depend on sophisticated compiler technology to manage complicated instruction
interdependencies.
Pipelining is employed so that all parts of the processing and memory systems can operate continuously.
Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is
being fetched from memory.
The memory interface has been designed to allow the performance potential to be realised without
incurring high costs in the memory system. Speed critical control signals are pipelined to allow system
control functions to be implemented in standard low-power logic, and these control signals facilitate the
exploitation of the fast local access modes offered by industry standard dynamic
Configuration Bits for Backward Compatibility
The other two inputs, PROG32 and DATA32 are used for backward compatibility with earlier ARM
processors (see 10.0 Appendix - Backward Compatibility) but should normally be set to 1. This configuration
extends the address space to 32 bits, introduces major changes in the programmer's model as described
below and provides support for running existing 26 bit programs in the 32 bit environment. This mode is
recommended for compatibility with future ARM processors and all new code should be written to use
only the 32 bit operating modes.
Because the original ARM instruction set has been modified to accommodate 32 bit operation there are
certain additional restrictions which programmers must be aware of. These are indicated in the text by the
words shall and shall not. Reference should also be made to theARM Application Notes “Rules for ARM Code
Writers” and “Notes for ARM Code Writers” available from your supplier.
Operating Mode Selection
ARM7 has a 32 bit data bus and a 32 bit address bus. The data types the processor supports are Bytes (8 bits)
and Words (32 bits), where words must be aligned to four byte boundaries. Instructions are exactly one
word, and data operations (e.g. ADD) are only performed on word quantities. Load and store operations
can transfer either bytes or words
Programmer's Model
ARM7 supports six modes of operation:
(1) User mode (usr): the normal program execution state
(2) FIQ mode (fiq): designed to support a data transfer or channel process
(3) IRQ mode (irq): used for general purpose interrupt handling
(4) Supervisor mode (svc): a protected mode for the operating system
(5) Abort mode (abt): entered after a data or instruction prefetch abort
(6) Undefined mode (und): entered when an undefined instruction is executed
Mode changes may be made under software control or may be brought about by external interrupts or
exception processing. Most application programs will execute in User mode. The other modes, known as
privileged modes, will be entered to service interrupts or exceptions or to access protected resources.
Figure 6: Format of the Program Status Registers (PSRs)
The format of the Program Status Registers is shown in Figure 6: Format of the Program Status Registers
(PSRs). The N, Z, C and V bits are the condition code flags. The condition code flags in the CPSR may be
changed as a result of arithmetic and logical operations in the processor and may be tested by all
instructions to determine if the instruction is to be executed.
The I and F bits are the interrupt disable bits. The I bit disables IRQ interrupts when it is set and the F bit
disables FIQ interrupts when it is set. The M0, M1, M2, M3 and M4 bits (M[4:0]) are themode bits, and these
determine the mode in which the processor operates. The interpretation of the mode bits is shown inTable
2: The Mode Bits. Not all combinations of the mode bits define a valid processor mode. Only those explicitly
described shall be used.
The bottom 28 bits of a PSR (incorporating I, F and M[4:0]) are known collectively as the control bits. The
control bits will change when an exception arises and in addition can be manipulated by software when the
processor is in a privileged mode. Unused bits in the PSRs are reserved and their state shall be preserved
when changing the flag or control bits. Programs shall not rely on specific values from the reserved bits
when checking the PSR status, since they may read as one or zero in future processors
ARM7 Data Sheet
Exceptions
Exceptions arise whenever there is a need for the normal flow of program execution to be broken, so that
(for example) the processor can be diverted to handle an interrupt from a peripheral. The processor state
just prior to handling the exception must be preserved so that the original program can be resumed when
the exception routine has completed. Many exceptions may arise at the same time.
ARM7 handles exceptions by making use of the banked registers to save state. The old PC and CPSR
contents are copied into the appropriate R14 and SPSR and the PC and mode bits in the CPSR bits are forced
to a value which depends on the exception. Interrupt disable flags are set where required to prevent
otherwise unmanageable nestings of exceptions. In the case of a re-entrant interrupt handler, R14 and the
SPSR should be saved onto a stack in main memory before re-enabling the interrupt; when transferring the
SPSR register to and from a stack, it is important to transfer the whole 32 bit value, and not just the flag or
control fields. When multiple exceptions arise simultaneously, a fixed priority determines the order in
which they are handled. The priorities are listed later in this chapter.
Instruction Set - LDR, STR
Offsets and auto-indexing
The offset from the base may be either a 12 bit unsigned binary immediate value in the instruction, or a
second register (possibly shifted in some way). The offset may be added to (U=1) or subtracted from (U=0)
the base register Rn. The offset modification may be performed either before (pre-indexed, P=1) or after
(post-indexed, P=0) the base is used as the transfer address.
The W bit gives optional auto increment and decrement addressing modes. The modified base value may
be written back into the base (W=1), or the old base value may be kept (W=0). In the case of post-indexed
addressing, the write back bit is redundant and is always set to zero, since the old base value can be retained
by setting the offset to zero. Therefore post-indexed data transfers always write back the modified base. The
only use of the W bit in a post-indexed data transfer is in privileged mode code, where setting the W bit
forces non-privileged mode for the transfer, allowing the operating system to generate a user address in a
system where the memory management hardware makes suitable use of this hardware.
Coprocessor Interface
The functionality of the ARM7 instruction set may be extended by the addition of up to 16 external
coprocessors. When the coprocessor is not present, instructions intended for it will trap, and suitable
software may be installed to emulate its functions. Adding the coprocessor will then increase the system
performance in a software compatible way. Note that some coprocessor numbers have already been
assigned. Contact ARM Ltd for up to date information