20-10-2012, 05:43 PM
Programmable Logic Devices
PLD.pdf (Size: 415.25 KB / Downloads: 393)
The need for getting designs done quickly has led to the creation and evolution
of Programmable Logic devices. The idea began from Read Only Memories
(ROM) that were just an organized array of gates and has evolved into System
On Programmable Chips (SOPC) that use programmable devices, memories and
configurable logic all on one chip.
This chapter shows the evolution of basic array structures like ROMs into
complex CPLD (Complex Programmable Logic Devices) and FPGAs (Field
Programmable Gate Array). This topic can be viewed from different angles, like
logic structure, physical design, programming technology, transistor level,
software tools, and perhaps even from historic and comerical aspects. However
our treatment of this subject is more at the structural level. We discuss gate
level structures of ROMs, PLAs, PALs, CPLDs, and FPGAs. The material is at
the level needed for understanding configuration and utilization of CPLDs and
FPGAs in digital designs.
Read Only Memories
We present structure of ROMs by showing the implementation of a 3-input 4-
output logic function. The circuit with the truth table shown in Figure 4.1 is to
be implemented.
Basic ROM Structure
The simplest way to implement the circuit of Figure 4.1 is to form its minterms
using AND gates and then OR the appropriate minterms for formation of the
four circuit outputs. The circuit requires eight 3-input AND gates and four OR gates that can take up-to eight inputs. It is easiest to draw this structure in an
array format as shown in Figure 4.2.
NOR Implementation
Since realization of AND and OR gates in most technologies are difficult and
generally use more delays and chip area than NAND or NOR implementations,
we implement our example circuit using NOR gates. Note that a NOR gate with
complemented outputs is equivalent to an OR, and a NOR gate with
complemented inputs is equivalent to an AND gate. Our all NOR
implementation of Figure 4.4 uses NOR gates for generation of minterms and
circuit outputs. To keep functionality and activity levels of inputs and outputs
intact, extra inverters are used on the circuit inputs and outputs. These
inverters are highlighted in Figure 4.4. Although NOR gates are used, the left
plane is still called the AND-plane and the right plane is called the OR-plane.
Distributed Gates
Hardware implementation of the circuit of Figure 4.4 faces difficulties in routing
wires and building gates with large number of inputs. This problem becomes
more critical when we are using arrays with tens of inputs. Take for example, a
circuit with 16 inputs, which is very usual for combinational circuits. Such a
circuit has 64k (216) minterms. In the AND-plane, wires from circuit inputs
must be routed to over 64,000 NOR gates. In the OR-plane, the NOR gates
must be large enough for every minterm of the function (over 64,000 minterms)
to reach their inputs.
Such an implementation is very slow because of long lines, and takes too
much space because of the requirement of large gates. The solution to this
problem is to distribute gates along array rows and columns.
In the AND-plane, instead of having a clustered NOR gate for all inputs to
reach to, the NOR gate is distributed along the rows of the array. In Figure 4.4,
the NOR gate that implements minterm 3 is highlighted. Distributed transistorlevel
logic of this NOR gate is shown in Figure 4.5. This figure also shows a
symbolic representation of this structure.
Array Programmability
For the a, b and c inputs, the structure shown in Figure 4.4 implements w, x, y
and z functions. In this implementation, independent of our outputs, we have
generated all minterms of the three inputs. For any other functions other than
w, x, y and z, we would still generate the same minterms, but use them
differently. Hence, the AND-plane with which the minterms are generated can
be wired independent of the functions realized. On the contrary, the OR-plane
can only be known when the output functions have been determined.