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1.2 Retinal Implantation:
A retinal implant is a biomedical implant technology currently being developed
by a number of private companies and research institutions worldwide.
The first application of an implantable stimulator for vision restoration was
developed by Drs. Brindley and Lewin in 1968. The implant is meant to
partially restore useful vision to people who have lost their vision. There
are two types of retinal implants namely epiretinal implant and subretinal
implant.
Epiretinal Implant :
Epiretinal implants sit in the inner surface of the retina. They are advantageous
as they bypass a large portion of the retina. It could provide visual
perception to individuals with retinal diseases extending beyond the photoreceptor
layer. The implants receive input from a camera and processing unit (E.g. on glasses). Electrodes from the implants electrically stimulate
the ganglion cells and axons at the start of the optic nerve.
Subretinal Implant :
Subretinal implants sit on the outer surface of the retina, between the photoreceptor
layer and the retinal pigment epithelium, directly stimulating retinal
cells and relying on the normal processing of the inner and middle retinal
layers. It has a simpler design .It replace damaged rods and cones by Silicon
plate carrying 1000s of light-sensitive micro photodiodes each with a stimulation
electrode. Light from image activates the micro photodiodes, the
electrodes inject currents into the neural cells.
Among the above implant methods, the epiretinal implant has features that
the image resolution can be high because the stimulus signal can be directly
conducted to neuron cells and that living retinas are not seriously damaged.
Trade off for the two types is that, Subretinal Implant uses the entire retina
(except the rods/cones). Epiretinal Implant does not; it must replace the
function of entire retina and convert light to neural code. But the input to
the Epiretinal Implant is more easily controlled (external camera).
ARTIFICIAL RETINA
USING THIN FILM
TRANSISTORS
2.1 Operation
Artificial Retina using Thin-Film Transistors (TFTs) is fabricated on transparent
and flexible substrates; it uses the same fabrication processes as conventional
poly-Si TFTs and encapsulated using SiO2, in order to perform in
corrosive environments. Although the artificial retina is fabricated on the
glass substrate here to confirm the elementary functions, it can be fabricated
on the plastic substrate. The artificial retina using TFTs is shown in Figure
2.1.
2.2.1 ION Doping Techniques
Figure 2.3 shows a schematic diagram of the new I/D system which is one
of the non-mass-separated implanters. 5 percent PH3 or 5 percent B2H6
diluted by hydrogen is used for the doping gas and an RF plasma is formed
in the chamber by RF power with a frequency of 13.56 MHz
Ions from discharged gas are accelerated by an extraction electrode and an
acceleration electrode and are implanted into the substrate. Main features
of this system are:
1) A large beam area (over 300 mm square)
2)A high accelerating voltage (maximum: 110 KeV)
With this system, impurities can be implanted over the entire 300 mm
square substrate with a maximum accelerating voltage of over 110 KeV which
is sufficient for implanting impurities through the 150nm SiO2 gate insulator.
On the other hand, the conventional non-mass-separated I/D techniques are
severely limited in beam area, which is about 150 mm in diameter. Furthermore,
they are incapable of implanting impurities through the gate insulator
since the accelerating voltages are less than 10 KeV. Consequently, the gate
insulator must be removed prior to implantation, which can result in failure
from surface contamination or breakdown between gate electrodes and source
and drain regions.
2.2.1.1 Self Aligned structure and TFT charecteristics
S/A TFTs and non-S/A TFTs with 25 nm thick as-deposited channel poly-Si
r31 were fabricated on the glass substrates, and the new I/D technique was
used to achieve a self-aligned structure. Schematic cross sectional views of
a S/A TFT and a non-S/A TFT are illustrated in Figure 2.4(a) and 2.4(b),
respectively. Since the parasitic capacitance between the gate electrode and
source and drain regions of a S/A TFT is estimated to be only about 2 -5
percent that of a non-S/A TFT, high speed operation can be expected.