13-11-2012, 01:54 PM
ASIC DESIGN FLOW
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ASIC Project
• ASIC design team (Project leader, designers for different tasks)
• Information share with closely related projects/design teams
(software, analog HW design, system design) - Documentation!
• ASIC project is a part of bigger project - Scheduling is important!
• Design flow must be defined and approved
ASIC Modeling
• The goal is to build a simulatable (behavioral) VHDL model
corresponding to the specification.
• The function of the model is verified by using a VHDL test bench
• Architecture design
• Model validation ok
Logic design
Naming rules
• Use meaningful names for signals, ports, functions and parameters.
For example, do not use ra for a RAM address bus. Instead, use
ram_addr or RamAddr (capital letters can also be used).
• If your design uses several parameters, use short but descriptive
names.
• Use the name clk for the clock signal. If there is more than one
clock in the design, use clk as the prefix for all clock signals (for
example clk4m, clk8m).
• Use the same name throughout the hierarchy for all clock signals
that are driven from the same source.
• For active low signals, end the signal name with an underscore
followed by a lowercase character x.
• Use the name reset for reset signals. For active low resets use the
name reset_x.
• For multibit buses, use (y downto x) ordering of bits.
Guidelines for clocks and resets
• Digital ASICs must be designed to be synchronous when possible.
This must be considered, when VHDL for synthesis is written. The
main benefits of synchronous design are:
• Timing problems are avoided. Only the propagation of signals
to the next register during one clock cycle must be verified.
• Most of the problems with hazards are avoided.
• The X-states and glitches in gated and multiplexed clocks are
avoided.
• It is easier to test a synchronous circuit than an asynchronous
one.
• Static timing analysis is possible.
• Avoid internally generated resets
• Make sure your registers are controlled only by a single reset signal.
• Avoid internally generated, conditional resets if possible. Generally,
all the registers in the macro should be reset at the same time. This
approach makes analysis and design much simpler and easier.
• If conditional reset is required, create a separate signal for the reset
signal, and isolate this in a separate module. This approach results in
more readable code and improves synthesis results.