04-03-2013, 05:00 PM
ASIC DESIGN
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UNIT I
INTRODUCTION TO ASICS, CMOS LOGIC AND ASIC
LIBRARY DESIGN 9
Types of ASICs - Design flow - CMOS transistors CMOS Design rules - Combinational Logic
Cell – Sequential logic cell - Data path logic cell - Transistors as Resistors - Transistor
Parasitic Capacitance- Logical effort –Library cell design - Library architecture .
UNIT II
PROGRAMMABLE ASICS, PROGRAMMABLE ASIC LOGIC CELLS
AND PROGRAMMABLE ASIC I/O CELLS
Anti fuse - static RAM - EPROM and EEPROM technology - PREP benchmarks - Actel ACT
- Xilinx LCA –Altera FLEX - Altera MAX DC & AC inputs and outputs - Clock & Power inputs
- Xilinx I/O blocks.
UNIT III
PROGRAMMABLE ASIC INTERCONNECT, PROGRAMMABLE ASIC
DESIGN SOFTWARE AND LOW LEVEL DESIGN ENTRY
Actel ACT -Xilinx LCA - Xilinx EPLD - Altera MAX 5000 and 7000 - Altera MAX 9000 - Altera
FLEX –Design systems - Logic Synthesis - Half gate ASIC -Schematic entry - Low level
design language - PLA tools -EDIF- CFI design representation.
UNIT IV
LOGIC SYNTHESIS, SIMULATION AND TESTING 9
Verilog and logic synthesis -VHDL and logic synthesis - types of simulation -boundary scan
test - fault simulation - automatic test pattern generation.
UNIT V
ASIC CONSTRUCTION, FLOOR PLANNING, PLACEMENT AND
ROUTING 9
System partition - FPGA partitioning - partitioning methods - floor planning - placement -
physical design flow –global routing - detailed routing - special routing - circuit extraction -
DRC