28-05-2012, 11:24 AM
ASIC Design Flow Tutorial Using Synopsys Tools
ASIC Design Flow Tutorial.pdf (Size: 4.52 MB / Downloads: 83)
Introduction
Integrated Circuits are made from silicon wafer, with each wafer holding hundreds of die.
An ASIC is an Application Specific Integrated Circuit. An Integrated Circuit designed
is called an ASIC if we design the ASIC for the specific application. Examples of ASIC
include, chip designed for a satellite, chip designed for a car, chip designed as an
interface between memory and CPU etc. Examples of IC’s which are not called ASIC
include Memories, Microprocessors etc. The following paragraphs will describe the types
of ASIC’s.
1. Full-Custom ASIC: For this type of ASIC, the designer designs all or some of
the logic cells, layout for that one chip. The designer does not used predefined
gates in the design. Every part of the design is done from scratch.
2. Standard Cell ASIC: The designer uses predesigned logic cells such as AND
gate, NOR gate, etc. These gates are called Standard Cells. The advantage of
Standard Cell ASIC’s is that the designers save time, money and reduce the risk
by using a predesigned and pre-tested Standard Cell Library. Also each Standard
Cell can be optimized individually. The Standard Cell Libraries is designed using
the Full Custom Methodology, but you can use these already designed libraries in
the design. This design style gives a designer the same flexibility as the Full
Custom design, but reduces the risk.
CMOS Technology
In the present decade the chips being designed are made from CMOS technology. CMOS
is Complementary Metal Oxide Semiconductor. It consists of both NMOS and PMOS
transistors. To understand CMOS better, we first need to know about the MOS (FET)
transistor.
MOS Transistor
MOS stands for Metal Oxide Semiconductor field effect transistor. MOS is the basic
element in the design of a large scale integrated circuit is the transistor. It is a voltage
controlled device. These transistors are formed as a ``sandwich'' consisting of a
semiconductor layer, usually a slice, or wafer, from a single crystal of silicon; a layer of
silicon dioxide (the oxide) and a layer of metal. These layers are patterned in a manner
which permits transistors to be formed in the semiconductor material (the ``substrate'');
The MOS transistor consists of three regions, Source, Drain and Gate. The source and
drain regions are quite similar, and are labeled depending on to what they are connected.
The source is the terminal, or node, which acts as the source of charge carriers; charge
carriers leave the source and travel to the drain. In the case of an N channel MOSFET
(NMOS), the source is the more negative of the terminals; in the case of a P channel
device (PMOS), it is the more positive of the terminals. The area under the gate oxide is
called the ``channel”. Below is figure of a MOS Transistor.
Power Dissipation in CMOS IC’s
The big percentage of power dissipation in CMOS IC’s is due to the charging and
discharging of capacitors. Majority of the low power CMOS IC designs issue is to reduce
power dissipation. The main sources of power dissipation are:
1. Dynamic Switching Power: due to charging and discharging of circuit
capacitances
A low to high output transition draws energy from the power supply
A high to low transition dissipates energy stored in CMOS transistor.
Given the frequency ‘f’, of the low-high transitions, the total power drawn
would be: load capacitance*Vdd*Vdd*f
2. Short Circuit Current: It occurs when the rise/fall time at the input of the gate is
larger than the output rise/fall time.
3. Leakage Current Power: It is caused by two reasons;
a. Reverse-Bias Diode Leakage on Transistor Drains: This happens in
CMOS design, when one transistor is off, and the active transistor charges
up/down the drain using the bulk potential of the other transistor.
Example: Consider an inverter with a high input voltage, output is low
which means NMOS is on and PMOS is off. The bulk of PMOS is
connected to VDD. Therefore there is a drain-to –bulk voltage –VDD,
causing the diode leakage current.
b. Sub-Threshold Leakage through the channel to an ‘OFF’ transistor/device.
CMOS Transmission Gate
A PMOS transistor is connected in parallel to a NMOS transistor to form a Transmission
gate. The transmission gate just transmits the value at the input to the output. It consists
of both NMOS and PMOS because, PMOS transistor transmits a strong ‘1’ and NMOS
transistor transmits a strong ‘0’. The advantages of using a Transmission Gate are:
1. It shows better characteristics than a switch.
2. The resistance of the circuit is reduced, since the transistors are connected in parallel.