01-08-2014, 10:29 AM
HIGH SPEED CARRY SAVE MULTIPLIER BASED LINEAR
CONVOLUTION USING VEDIC MATHAMATICS
HIGH SPEED CARRY.pdf (Size: 343.98 KB / Downloads: 18)
INTRODUCTION
In this paper, carry save multiplier
architecture is developed using Urdhva-Tiryagbhyam
sutra. This sutra is applied to perform multiplication of
size NXN.
Linear convolution which is a fundamental
computation in Linear time-invariant (LTI) systems is
implemented using Verilog HDL. Simulation and
Synthesis are verified in Xilinx 10.1 ISE.
In general, multiplications are complex and
slow in operation. The overall speed in multiplication
depends on number of partial products generated,
shifting the partial products based on bit position and
summation of partial products. In carry save
multiplier, the carry bits are passed diagonally
downwards, which requires a vector merging
adder to obtain final sum of all the partial products[1].
In convolution, fundamental computations includes
multiplication and addition of input and impulse
signals or samples[2]
CONVOLUTION
Linear and time-invariant systems are an important
class of systems and has significant signal
processing applications.
5 CONCLUSION
In this paper, Linear convolution of discrete finite
length sequences is performed using carry save
multiplier based an Vedic sutra and an adder. The
proposed multiplier using Vedic mathematics results
in high computational speed and minimum critical
path ,hence, less delay, when compared to simple
multiplier. The maximum computational speed of
Linear Convolution is 15.38 ns. The delay can further
be reduced by optimizing adder