29-05-2012, 11:39 AM
AVR
AVR.ppt (Size: 96 KB / Downloads: 316)
Modern RISC architecture: Compact and FAST.
Tuned for high level languages.
Consistent architecture across entire line.
Small AVR are subsets of larger chips: Same hardware and code works across all chips.
I/O structure reduces need for external components.
Flash based, ultra trivial downloading of code.
AVR RISC Architecture
Single Cycle Instructions: 8mhz = 8mips.
Large register file (32).
Every register an accumulator.
3 index register pairs
Register & IO are mapped in SRAM space.
everything (single unit price):
Attiny26 (2k, ADC, USI, 2 PWM, 2 ports) $2.58
ATmega16 (16k, ADC, etc, 4 ports) $7.74
ATmega128 (128k, 6 ports, oodles of stuff) $16.34
STK500 (development board) $79
ICE200 (In circuit emulator) $100
ATAVRISP (serial programmer) $29
Input example: Photo-detector
Schmitt trigger inputs on all lines.
No additional signal conditioning needed.
Stable, well defined trip points.
Basic circuit works well for Quadrature encoders.