03-11-2016, 04:12 PM
1464203102-AXI54.pdf (Size: 1.01 MB / Downloads: 20)
Abstract— The ARM (Advanced RISC Machine) has developed AMBA (Advanced Microcontroller Bus Architecture) bus protocol
which is widely used by System-on-Chip (SoC) designers. Systems-on-Chip are one of the biggest challenges engineers ever faced
which result a mix of microprocessor, memories, buses architectures, communication standards, protocol and interfaces.AMBA buses
act as the high-performance system backbone bus. It supports the efficient connection of processors, on-chip memories and off-chip
external memory interfaces. APB and AHB come under AMBA standard. ARM has come up with its latest on chip bus transfer bus
protocol, called AMBA AXI. AXI stands for Advanced Xtensible Interface.From a technology perspective, AMBA AXI (Advanced
eXtensible Interface) provides the means to perform low latency, high bandwidth on chip communication between multiple masters
and multiple slaves. Moving one stage further, from an implementationperspective, configurability and programmability are becoming
vital to ensuring IP can be tuned for a given application or project requirement.
Introduction
Interconnect provides efficient connection between master (e.g. ARM processors, Direct Memory Access (DMA) or Digital Signal
Processor (DSP)) and slave (e.g. external memory interface, APB bridge and any internal memory).
The Interconnect is a highly configurable RTL component, which provides the entire infrastructure require to connect
number of AXI masters to a number of AXI slaves. This infrastructure is an integral part of an AXI-based system.
Architecture of interconnect is highly modular with each of the routers and associated control logic partitioned on a perchannel
basis. It ensures, which bus master is allowed to initiate data transfers depending on highest priority or fair access.
As AXI provides many features such as out of order completion, interleaving; interconnect is responsible to take care of
interleaving and out of order. The block level RTL code is automatically configured from a system description file to specify no of
master, slave , width of address bus hence interconnect is implemented depending on the application requirements.
AXI Interconnect takes care of all 5 channels, using which data transfer between master and slave take place.
Features of Interconnect
The ACI features are:
• It is compliant with the AMBA AXI Protocol v1.0 Specification
• It multiplexes and demultiplexes data and control information between connected masters and slaves
• It enforces the AXI ordering rules that govern the flow of data and control information on different channels
• It has a multi-layer capability to allow multiple masters to access different slaves simultaneously
• Out-of-order data support
• You can configure the following parameters:
— number of master and slave interfaces
— The ID width of each slave interface
— The read and write acceptance capability of each slave interface
— The write issuing capability of each master interface
— The write interleave capability of each master interface
AIM OF THE PROJECT
The aim of the project is to Design an AXI interconnect between four master and four slave interfaces.
OBJECTIVE
Design related TASKS
Design related tasks that were performed in the project are:
The Architecture of the design was thought by considering the specifications and then Block Diagram was prepared.
The Block Diagram was divided into sub- modules which are communicating with each other.
Block Diagram of 5 channels are made
Write Address Channel
Read Address Channel
Write Data Channel
Read Data channel
Write Response Channel
Block diagram was analyzed number of times for the correctness of the architecture
After the designing ,Verilog and VHDL coding is done of low level modules used in all the channels
These low level modules are combined in a top module for all the block diagram of the 5 channels
All codes corresponding to these block diagrams have been combined in top level module which constitutes the whole
interconnect
Whole Design was synthesized to check for the errors.
SPECIFICATIONS
Design the AMBA AXI INERCONNECT for four Ports in which each port behave as AXI based master interfaces and slave
interfaces.
32 Bit Address Bus and 64 Bit Data Bus
Configurable Port Addresses (Slave size is configurable)
One outstanding transaction
Support all type of Burst Transaction (Wrap, INCR, Fixed)
Support Normal and Locked Operation
Support 200 MHz on VIRTEX 5
Following is the priority considered for masters :
Master0 > Master1 > Master2 > Master3
Master generates and drives transaction onto the bus.
Slave device accepts transaction from any master.
Interconnect routes the AXI requests and responses between AXI masters and AXI slaves. Passive Monitoring, Checking
and Collection of functional coverage specifically targeted at the AXI Interconnect are the mains functions of Interconnect.
Interconnect consist of 5 channels:
Read address channel: This channel gives information about Transaction ID for read operation, address of slave,
Burst length along with size and type, valid signal to indicate control information is valid and ready.
Write address channel: This channel gives information about Transaction ID for write operation, address of slave,
Burst length along with size and type, valid signal to indicate control information is valid and ready
Read data channel: This channel gives information about Transaction ID for read data, read data, read response
along with ready and valid signal
Write data channel: This channel gives information about Transaction ID for write data, write data with strobe
information ready and valid signal
Write response channel: This channel gives information about Transaction ID for write data, write response along
with ready and valid signal
Default slave is used when there is no fully –decoded address map physically present. There can be address at
which there are no slave to respond to the transaction, then interconnect effectively routes the access to a default slave. As in
case of AXI protocol it is necessary that all transaction must be complete even there is any error.
ADDRESS CHANNEL
The address channel conveys address information along with control signal from master to the slave. AXI support different address
buses for write and read transfer, so that through put of the system is increased. Both channels (read/write) have same signals included
in the address channel.
The address channel includes address bus which is 32 bit, length of burst; it gives exact no of data transfer in burst, size of
transfer to indicate bytes in one burst, burst type which is WRAP, FIXED and INCR, lock information along with valid and ready
signals
Following points explain the detailed functioning of Address channel interconnects
1. When Master sends valid Address and control signal Slave Decoder decodes that address and generate output to indicate
request from master to slave.
2. Decoder has five output bits, each bit indicates request to particular slave S0, S1, S2, S3 and default slave.
3. Each decoder output is given to the each switching control unit as request.
4. S0 is given to switching control unit for slave0; S1 is to switching control unit for slave1 and so on.
5. Thus each switching control unit receives four request from four masters It gets request from each master for NORMAL and
LOCKED operation, depending on priority it will grant that slave to appropriate master.
Path select will enable granted master address channel other channel will remain disabled.
If the select signal is 1000 then master0 address channel is selected
If the select signal is 0100 then master1 address channel is selected
If the select signal is 0010 then master 2 address channel is selected
If the select signal is 0001 then master 3 address channel is selected
6. Slave will accept now valid address and control signals.
7. Slave sends ready signal back to the granted master. This ready signal is given to granted master by ANDing logic. This is
done in same way as address and control signals are routed towards the slave.
Thus Master receives ready from slave.