07-08-2014, 11:00 AM
DESIGN OF ON-CHIP BUS OCP PROTOCOL WITH BUS FUNCTIONALITIES
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INTRODUCTION
In recent days, the development of SOC chips
and the reusable IP cores are given higher priority
because of its less cost and reduction in the period of
Time-to- Market. So this enables the major and very
sensitive issue such as interfacing of these IP cores.
These interfaces play a vital role in SOC and should
be taken care because of the communication
between the IP cores property. The communication
between the different IP cores should have a lossless
data flow and should be flexible to the designer too.
The design of on-chip buses can be divided into
two parts: bus interface and bus architecture. The bus
interface involves a set of interface signals and their
corresponding timing relationship, while the bus
architecture refers to the internal components of buses
and the interconnections among the IP cores.
The AMBA AHB[2], which is mainly a
shared bus composed of multiplexors, it can be
permitted to a design with small number of IP Cores.
When the IP Cores increases then the overall
performance can be reduced
DESCRIPTION OF OPEN CORE PROTCOL(OCP)0
The Open Core Protocol (OCP) is a core
centric protocol which defines a high-performance,
bus- independent interface between IP cores that
reduces design time, design risk, and manufacturing
FUNCTIONALITIES OF ON CHIP BUS
The advanced bus functionalities supported by this
protocol are
A) Simple transactions B) Burst transactions
C) Out-of-order transactions
D) Pipelined transactions
A) Simple transactions: Allows the simple read
and write operations.
B) Burst transactions:
The burst transactions allow the grouping of
multiple transactions that have a certain address
relationship, and can be classified into multi-request
burst and single-request burst according to how many
times the addresses are issued. FIGURE 2 shows
the two types of burst read transactions
RESULTS
The simulation results when 4 masters and 4
slaves are used are shown below where all masters
can issue all transactions.
In the figure 5- for simple write
operation the corresponding control input is 001 as
shown in Table1 and the given data(mwdata signal)
will be stored in the applied address location
(maddr) .The selection of master will be done by
high m_enable signal.Then the arbiter will generates
M grantsignal for selected master. As maddr
and mwdata signals passes through the
multiplexors and converted to multiplexed signals.
The decoder will select any one of the slave
according to maddr,then ihe simple write operation is
CONCLUSION
Cores with OCP interfaces and OCP interconnect
systems enable true modular, plug-and-play
integration; allowing the system integrators to
choose cores optimally and the best application
interconnect system. This allows the designer of the
cores and the system to work in parallel and shorten
design times. In addition, not having system logic in
the cores allows the cores to be reused with no
additional time for the core to be re-created.
Depending upon the real time application these
intellectual properties can be used.
The simulation result shows that the
communication between different IP cores using
OCP is proper. The OCP is designed and
synthesized and observed HDL Synthesis, final
Report, device utilization and Timing summary .