20-08-2012, 03:54 PM
Adaptive Keeper Design for Dynamic Logic Circuits Using Rate Sensing Technique
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Abstract
The increasing variability in device leakage has made
the design of keepers for wide OR structures a challenging task.
The conventional feedback keepers (CONV) can no longer improve
the performance of wide dynamic gates for the future technologies.
In this paper, we propose an adaptive keeper technique called rate
sensing keeper (RSK) that enables faster switching and tracks the
variation across different process corners. It can switch upto 1.9
faster (for 20 legs) than CONV and can scale upto 32 legs as against
20 legs for CONV in a 130-nm 1.2-V process. The delay tracking
is within 8% across the different process corners.We demonstrate
the circuit operation of RSK using a 32 8 register file implemented
in an industrial 130-nm 1.2-V CMOS process. The performance
of individual dynamic logic gates are also evaluated on
chip for various keeper techniques. We show that the RSK technique
gives superior performance compared to the other alternatives
such as Conditional Keeper (CKP) and current mirror-based
keeper (LCR).
INTRODUCTION
WIDE OR structures are typically used in the read path
of register files, L1 caches, match lines of TCAMs,
flash memories and PLAs. In most of the applications the worst
case requirement would be to sense the difference between the
leakage state where all the pulldown legs are leaky and the
ON state where only one of the legs is ON. The increase in the
variability and magnitude of the leakage current has become a
major bottleneck in realizing such wide OR gates. Especially,
in case of dynamic logic gates, the robustness of the dynamic
node has to be guaranteed across different process corners
without significant loss in the performance. For this purpose
the dynamic gates use a feedback keeper to support the leakage
at the dynamic node during the evaluation phase. However, the
feedback keeper produces a large contention current during
evaluation phase.
RATE SENSING KEEPER
The rate sensing keeper (RSK) technique works based on the
difference in the rate of change of voltage at the dynamic node
of the gate during the ON and the leakage
condition. A reference rate , which is the average of the
two rates is used to control the state of the keeper. The fact that
the keeper is OFF during the start of the evaluation phase and
the adaptive control of the keeper strength based on the process
corner helps RSK to achieve higher speed and better tracking,
respectively.
PVT Adaptive Bias Generation
Process variations have three components namely, inter-die
variations that is common to all the gates on the chip, spatially
correlated intra-die variation which is common to all gates
within a spatially correlated region and random intra-die variations
which is uncorrelated from transistor to transistor.The
RSK uses a replica circuit based on a dummy OR gate to generate
the analog bias voltage VBIAS that controls the reference
rate. One replica is used for every spatially correlated region
that compensates for the global and the spatially correlated intra
die variations as the gates within the same region will have the
same shift in the threshold voltage. The random variations in
the pull down legs of the domino gates will average out for
gates of larger width. The impact of random variations in the
bias transistor M4 (Fig. 5) can be minimized by increasing its
length. Since the required reference rate varies with different
process corners, the bias voltage should also vary accordingly.
CONCLUSION
In this paper we proposed an adaptive keeper technique called
RSK-based on the cross couple structure proposed in [10] and
[11]. RSK overcomes the limitations of process tracking in [10],
[11] by adaptively controlling the discharge rate of the complementary
node. The reduced contention current and tracking of
the global and spatially correlated local process variations enables
very high speed and process tolerant dynamic gates, respectively.
The reduced contention current during the evaluation
phase enables RSK to operate up to 1.7 faster than LCR
and 2 faster than CKP. The replica bias generation enables
the keeper to track the variation in process, voltage (supply and
noise) and temperature. The delay variation is within 8% across
the different process corners.