15-10-2012, 04:27 PM
Addressing mode
Addressing-mode.pdf (Size: 139.13 KB / Downloads: 161)
Addressing modes are an aspect of the instruction set architecture in most central processing unit (CPU) designs.
The various addressing modes that are defined in a given instruction set architecture define how machine language
instructions in that architecture identify the operand (or operands) of each instruction. An addressing mode specifies
how to calculate the effective memory address of an operand by using information held in registers and/or constants
contained within a machine instruction or elsewhere.
In computer programming, addressing modes are primarily of interest to compiler writers and to those who write
code directly in assembly language.
Caveats
Note that there is no generally accepted way of naming the various addressing modes. In particular, different authors
and computer manufacturers may give different names to the same addressing mode, or the same names to different
addressing modes. Furthermore, an addressing mode which, in one given architecture, is treated as a single
addressing mode may represent functionality that, in another architecture, is covered by two or more addressing
modes. For example, some complex instruction set computer (CISC) computer architectures, such as the Digital
Equipment Corporation (DEC) VAX, treat registers and literal/immediate constants as just another addressing mode.
Others, such as the IBM System/390 and most reduced instruction set computer (RISC) designs, encode this
information within the instruction. Thus, the latter machines have three distinct instruction codes for copying one
register to another, copying a literal constant into a register, and copying the contents of a memory location into a
register, while the VAX has only a single "MOV" instruction.
How many addressing modes?
Different computer architectures vary greatly as to the number of addressing modes they provide in hardware. There
are some benefits to eliminating complex addressing modes and using only one or a few simpler addressing modes,
even though it requires a few extra instructions, and perhaps an extra register.[1] It has proven much easier to design
pipelined CPUs if the only addressing modes available are simple ones.
Most RISC machines have only about five simple addressing modes, while CISC machines such as the DEC VAX
supermini have over a dozen addressing modes, some of which are quite complicated. The IBM System/360
mainframe had only three addressing modes; a few more have been added for the System/390.
When there are only a few addressing modes, the particular addressing mode required is usually encoded within the
instruction code (e.g. IBM System/390, most RISC). But when there are lots of addressing modes, a specific field is
often set aside in the instruction to specify the addressing mode.
Useful side effect
Some processors, such as Intel x86 and the IBM/390, have a Load effective address instruction. This performs a
calculation of the effective operand address, but instead of acting on that memory location, it loads the address that
would have been accessed into a register. This can be useful when passing the address of an array element to a
subroutine. It may also be a slightly sneaky way of doing more calculation than normal in one instruction; for
example, using such an instruction with the addressing mode "base+index+offset" (detailed below) allows one to add
two registers and a constant together in one instruction.