12-11-2012, 05:00 PM
Advanced Physical Models for Mask Data Verification and Impacts on Physical Layout Synthesis
Advanced Physical Models for Mask Data Verification and Impacts on Physical.pdf (Size: 196.78 KB / Downloads: 18)
Abstract
The proliferation and acceptance of reticle enhancement
technologies (RET) like optical proximity correction
(OPC) and phase shift masking (PSM) have significantly
increased the cost and complexity of sub-100 nm
photomasks. The photomask layout is no longer an exact
replica of the design layout. As a result, reliably verifying
RET synthesis accuracy, structural integrity, and
conformance to mask fabrication rules are crucial for the
manufacture of nanometer regime VLSI designs. In this
paper, we demonstrate a physical model based mask
layout verification system. The new system consists of an
efficient wafer-patterning simulator that is able to solve
the process physical equations for optical imaging and
resist development and hence can achieve high degree
accuracy required by mask verification tasks. It is able to
efficiently evaluate mask performance by simulating edge
displacement errors between wafer image and the
intended layout. We show the capabilities for hot spot
detection, line width variation analysis, and process
window prediction capabilities with a sample practical
layout. We also discuss the potential of the new physical
model simulator for improving circuit performance in
physical layout synthesis.
Introduction
The widespread acceptance of reticle enhancement
technologies for sub 0.1 um integrated circuit
manufacturing has dramatically complicated the mask
data and increased the cost of advanced photomasks [1].
The increase in pattern complexity due to optical
proximity correction, the tight requirements for critical
dimension (CD) control, and the difficulties in defect
inspection and repair all contribute to the manufacturing
cost increase. For phase shift masks (PSM), the problems
are compounded by additional requirements such as
controlling the etching of multiple materials, alignment of
multiple layers, and inspecting small defect with weak
signals.
Physical Model Based Mask Layout Verification Flow
the standard flow for reticle
enhancement and optical proximity correction, with
model based mask data verification block outlined with
gray shading. Here we consider model based OPC as an
independent module because it is also needed for all other
reticle enhancement techniques as well as standard binary
masks. The main manufacturing flow is shown on the left
hand side. The design layout from a customer is modified
with reticle enhancement, followed by model based OPC
to produce a set of mask geometry data that is suitable for
mask manufacturing. The model generation flow is shown
on the right, where a test layout is printed with the same
pattern transfer process to produce an experimental data
set for empirical model fitting. The resulting model can
then be used in the OPC engine to predict the wafer CD
error. From that, the amount of mask correction can be
calculated.
Proximity Induced Line Width Variation Statistics
Variations in line width due to lithography and etching
often limit the performance of a circuit. The line width
variation pattern changes as focus varies within allowed
process control limits. Existing OPC methodology is
aimed at reducing the line width variability at a nominal
focus point, without considering the potential impact of
focus change. In this case, physical model can be applied
to obtain more complete and meaningful line width
variation statistics by considering focus and other process
parameter variations, the result of which can be used for
performance optimization.