01-08-2012, 10:23 AM
Advanced Techniques in CMOS Logic Circuits
Advanced Techniques.pptx (Size: 175.82 KB / Downloads: 22)
Mirror circuit
Mirror circuits are based on series-parallel logic gates but are usually faster and have a more uniform layout
The important aspect of this observation is that there are equal number of input combination that produce 0’s and 1’s
The mirror image seen in the mirror will be the other side of the circuit
Every path between the output and a power supply rail consists of two resistance and a parasitic inter-FET capacitor
The Elmore time constant is of the form
τx=Cout(2*Rx)+Cx*Rx
where the subscript x is either n or p
Tr=2.2τp (rise time)
Tf=2.2 τn (fall time)
Clocked CMOS
It is composed of static logic circuit with tri-state output network is controlled by φ and ~φ
The clock signal is a periodic waveform with well defined period and frequency such that f=(1/t)
Show the clock φ and ~φ these are non-overlapping that is
φ * ~φ =O
Clocked CMOS is useful because we can synchronize the data flow through a logic cascade by controlling the internal operation of the gate
The output node cannot hold the charge on Vout very long due to a phenomenon called charge leakage
iout=in-ip
Dynamic CMOS logic circuits
A dynamic logic gate uses clocking and charge storage properties of MOSFETs to implement logic operations.
The feature of dynamic logic gate is that the result of calculation is valid only for short period of time.
Clock φ drive the complimentary pair transistors and these provide synchronization.
If clock is ‘0’ the circuit is precharge with ‘mp on’ and ‘mn off’
If clock is ‘1’ drive the circuit into the evaluation mode where ‘mp off’ and ‘mn on’
The problem in this is charge leakage eventually drops the vout to 0 which is incorrect logic value
To place the above problem minimum frequency stipulation on the clock