05-12-2012, 11:45 AM
All Digital Linear Voltage Regulator for Super- to Near-Threshold Operation
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Abstract
In this paper, an all digital push-pull linear voltage
regulator is proposed that consists of a digital error detector,
a voltage divider, a mode indicator, a pull device, and grouped
push devices. The digital regulator is suitable for super- to
near-threshold region operation by providing a variable output
voltage that ranges from 0.5 to 1 V in steps of 0.1 V. The maximum
load current is 100 mA for every output level. The current
efficiency is 99.8% with only 164.5 A quiescent current on UMC
65-nm standard CMOS technology. A response time constraint is
developed to provide a design guideline for (all) the digital control
system. It describes the correlation between required speed of
the digital control system, the output performance and the size of
the decoupling capacitor. A time interleaving control technique
is then proposed to have a tradeoff between output performance,
quiescent current, and the size of decoupling capacitor.
INTRODUCTION
F UTURE applications span from high-performance processors
and portable wireless applications, to sensor nodes
and medical implants [1]. Power has become the primary design
concern for all these applications. The full spectrum of
the supply voltage from super- to subthreshold region is explored
to enhance the power/energy efficiency. In order to provide
more flexibility on power control, scalable supply voltage
[2], [3] were presented which requires variable power supplies.
The emerging heterogeneous multicore and system-on-a-chip
(SoC) designs further complicate the power structure because
multiple adjustable power supplies can be demanded. Fully integration
of power supplies is also preferred to reduce the cost.
Switching converters [4]–[8] and linear regulators [9]–[15]
are two basic types of power supplies. Switching converters
can use capacitive (switched capacitor converter) or inductive
(buck converter) energy storage. Switched capacitor converter
[4] is usually used for low voltage and light load environment
whereas buck converters [5]–[8] are usually for large load environments.
Switching converters have the potential for more
than 90% power efficiency [5] and are capable of digital control.
DIGITAL CONTROLLED LINEAR REGULATOR
The digital controlled voltage regulator was first proposed
in [19]. It is designed to provide a variable regulated voltage
ranging from 1 to 0.5 V in steps of 0.1 V. The maximum load
current is 100 mA for every output voltage level. The idea of
the proposed digital controlled linear regulator is to replace the
analog building blocks shown in Fig. 1 with their digital counterparts.
The architecture of the proposed digital controlled linear regulator
is presented in Fig. 2. Push-pull topology as in [13] is
used. The major components are a digital error detector (DED),
a voltage divider, a mode indicator, a pull device, and grouped
push devices with their own drivers. The digital error detector
is the replacement of the analog error amplifier. The voltage divider,
the mode indicator and the grouped output devices are
designed for the purpose of variable output voltage. The analog
buffer in Fig. 1 is replaced by digital control logics and drivers
of the output devices.
Response Time Constraint
Discrete operation is the major drawback when using digital
control circuit for linear regulator. The control system cannot respond
to the change of the regulated voltage until next trigger.
If the trigger period is too long and the decoupling capacitor
is too small, the regulated voltage ripple will be large. The requirement
of the control loop response will be investigated in
this section in terms of the relationship between the control loop
response time, the size of the decoupling capacitor and the maximum
ripple of the regulated voltage.
Fig. 6 is the illustration of overshoot and undershoot of the
regulated voltage for analysis. is the target output voltage.
and specify the upper and lower bounds of voltage
ripple, respectively. The digital control system will be evaluated
separately for voltage overshoot and undershoot situations.
Simulation Results
The design uses UMC 65-nm standard CMOS technology
with only normal threshold voltage devices. The nominal supply
voltage is 1.1 V. The performance of the implemented regulator
is examined based on the response time constraint in Table IV.
Waveforms of post-layout simulation are shown in Fig. 7.
The size of the decoupling capacitor is 3 nF. Fig. 7(a) illustrates
output mode changing of the regulator with zero load. The simulated
step responses of the regulated voltage with full load are
shown in Fig. 7(b). The rise and fall time of the load current are
both 100 ps.
Ideally the regulated voltage should settle at the desired
output after the first undershoot. However, multiple overshoots
and undershoots can be observed in Fig. 7(b). It is because the
push current is designed to be a little larger since the equality
to the maximum load current cannot be guaranteed under
variations. The decoupling capacitor will be charged over the
desired voltage level even in the presence of the load current
and then activates another discharge operation. It can also be
observed from the figure that charging with no load creates the
largest overshoot whereas discharging with full load causes
the largest undershoot. It is consistent with the analysis in
Section II-B. Overall, the average of the regulated voltage is
almost equal to the desired output voltage level.
TECHNOLOGY MIGRATION DEMONSTRATION
One of the major advantages of digital circuits is the easiness
to migrate between different technology nodes. The proposed
digital controlled voltage regulator possesses the same
technology migration advantage since it is built from purely digital
behavior circuits except the passive voltage divider. Furthermore,
the proposed regulator is more beneficial from technology
advancing because of the performance gain. The response time
constraint discussed in Section II-B are easier to be met by faster
circuits in more advanced technology even with low cost small
decoupling capacitor.
The migration of the proposed digital controlled voltage regulator
only takes a few steps. First, simple logic gates such as
INV/NAND/NOR gates that compose most of the control system
are constructed for the target technology node. Then the voltage
controlled delay cell of DED requires a slight tuning for proper
delay versus voltage relationship. Finally, the output devices as
well as the drivers are resized to provide the target load current
and the migration task is completed.
EXPERIMENTAL RESULTS
The proposed digital controlled voltage regulator has been
implemented with UMC 65-nm standard CMOS technology.
Fig. 13 shows the post-layout simulation results of output
voltage error in 0.5 V stable states versus supply voltage at
different temperatures. Note that the error is not a fixed value
in every supply voltage/temperature combination. It may vary
in different operation times. However, a trend can still be
observed from the figure that the stable state error increases
along with supply voltage and temperature. It is consistent
with the analysis in Section III that increased supply voltage
and temperature both degrade the resolution of DED. The
analysis also reveals that the degradation of DED’s resolution
by supply voltage is larger than that by temperature. Hence, the
dependence of the error on supply voltage is much larger than
that on temperature as shown in the figure.
CONCLUSION
A fully digital controlled voltage regulator is presented.
Super- to near-threshold region operation is supported by
providing a variable regulated output ranging from 0.5 to 1 V
in steps of 0.1 V. The work consists of a digital error detector,
a voltage divider, a mode indicator, a pull device and grouped
push devices with their own drivers. The maximum load current
is designed (but not limited) to be 100 mA for every output
voltage. The measurement of the testchips fabricated on UMC
65-nm standard CMOS technology reports a current efficiency
of 99.8% with only 164.5 A quiescent current. A time interleaving
control technique is proposed as well to enhance the
output performance at the cost of increased quiescent current.
The area occupied by the digital control system of the regulator
is only about 300 m . A response time constraint that is
specific to (all) the digital control system is also presented. It
provides the design guideline for required speed of the control
system and the size of the decoupling capacitor.