19-02-2013, 03:23 PM
An Approach For Designing A Universal Asynchronous Receiver Transmitter (UART)
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Abstract
This paper describes the design of Universal Asynchronous Receiver and Transmitter (UART) using VHDL. A UART is a full duplex receiver/transmitter. It is the microchip with programming that controls a computer's interface to its attached serial devices. It handles the conversion between serial and parallel data. It is the most widely used serial data communication circuit ever. Whole process of serial transmission is based upon the principle of shift register.
INTRODUCTION
Universal Asynchronous Receiver Transmitter (UART) is generally used for better transmission of serial data that is it either transmit or receives data serially. It is a popular and widely used device for data communication in the field of telecommunication. There are different versions of UARTs in the industry. UART is an integrated circuit containing a transmitter(parallel to serial converter) and a receiver (serial to parallel converter) each clocked separately. It transmit 9600 to 38400 bps for transmitting data bit . Whole process of serial transmission is based upon the principle of shift register[14]. There are two primary forms of serial transmission: Synchronous and Asynchronous. Synchronous serial transmission requires that the sender and receiver share a clock with one another, or that the sender provide a strobe or other timing signal so that the receiver knows when to “read” the next bit of the data. In most form of Serial Synchronous Communication, if there is no data available at a given instant to transmit, a fill character must be sent instead so that data is always being transmitted. Asynchronous transmission allows data to be transmitted without the sender having to send a clock signal to the receiver. Instead, the sender and receiver must agree on timing parameters in advance and special bits are added to each word which are used to synchronize the sending and receiving units[16].
ROLE OF VHDL IN DESIGNING DIGITAL CIRCUITS
The design of the system at the gate level is more time consuming since the integrated circuit technology is more complex. Therefore the use of VHDL (Very High Speed Integrated circuit hardware Description Language) is preferred. VHDL can be used to describe and simulate the operation of digital circuits ranging from few gate to more complex gates. VHDL can be used for the behavioral level design implementation of a UART and it offers several advantages. These are the advantages of using VHDL to implement UART:
1. VHDL allows us to describe the function of the transmitter in a more behavioral manner rather than focus on its actual implementation at the gate level .
2. VHDL makes the design implementation easier to read and understand.
THEORY OF OPERATION
UART is generally consists of transmitter module, receiver module, baud-rate generator and control circuitAs shown in fig.(b) System-clock is used to produce baud_clock, which is generally 16 times baud-rate. Xmitter module converts parallel data input into serial data output and receiver module does vice versa. The basic functions of a UART are a microprocessor interface, double buffering of transmitter data, frame generation, parity generation, parallel to serial conversion, double buffering of receiver data, parity checking, serial to parallel conversion. In data transmission through UART, once the baud-rate has been established (prior to initial communication), both the transmitter and the receiver’s internal clock are set to the same frequency.
UART Receiver Functional Pins
The signals used by the receiver are given in the table 2. The receiver interfaces to the data bus dout[7:0] with the rdn signal. The controller can generate a rdn strobe if data_ready is true. The receiver is double buffered, allowing data to be held in the buffer register rbr[7:0] while data is shifted in serially into the receiver shift register rsr[7:0]. This provides the controller flexibility with bus read operations. The receiver detects the character frame and strips the start and stop bits. The no_bits_rcvd variable controls the word size. The clkdiv[3:0] register is used to control the time at which the data is decoded. The receiver uses the 16x local clock and decodes the value of start, data, and stop bits in the center of the data cells. To do this, the start bit initializes a count operation using clkdiv[3:0].