06-02-2013, 03:48 PM
An Area-Efficient Carry Select Adder Design by Sharing the Common Boolean Logic Term
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Abstract
In this paper, we proposed an area-efficient
carry select adder by sharing the common Boolean logic
term. After logic simplification and sharing partial
circuit, we only need one XOR gate and one inverter gate
in each summation operation as well as one AND gate
and one inverter gate in each carry-out operation.
Through the multiplexer, we can select the correct output
result according to the logic state of carry-in signal. In
this way, the transistor count in a 32-bit carry select
adder can be greatly reduced from 1947 to 960. Moreover,
the power consumption can be reduced from 1.26mw to
0.37mw as well as power delay product reduced from
2.14mw*ns to 1.28mw*ns.
INTRODUCTION
THE carry-ripple adder is composed of many cascaded
single-bit full-adders. The circuit architecture is simple
and area-efficient. However, the computation speed is slow
because each full-adder can only start operation till the
previous carry-out signal is ready. In the carry select adder, N
bits adder is divided into M parts. Each part of adder is
composed two carry ripple adders with cin_0 and cin_1,
respectively. Through the multiplexer, we can select the
correct output result according to the logic state of carry-in
signal. The carry-select adder can compute faster because the
current adder stage does not need to wait the previous stage’s
carry-out signal. The summation result is ready before the
carry-in signal arrives; therefore, we can get the correct
computation result by only waiting for one multiplexer delay
in each single bit adder. In the carry select adder, the carry
propagation delay can be reduced by M times as compared
with the carry ripple adder. However, the duplicated adder in
the carry select adder results in larger area and power
consumption.
SIMULATION COMPARISON RESULTS
We compare the circuit performance with three different
architectures, 32-bit carry ripple adder, 32-bit carry select
adder, and 32-bit area-efficient carry select adder that is
proposed in this paper. As for the transistor count, the
transistor count of our proposed area-efficient carry select
adder could be reduced to be very close to that of carry ripple
adder; however, the transistor count in the conventional carry
select adder is nearly double as compared with the proposed
design. This result shows that sharing common Boolean logic
term could indeed achieve a superior performance in aspect
of transistor count.
The area-efficient carry select adder can also achieve an
outstanding performance in power consumption. Power
consumption can be greatly saved in our proposed
area-efficient carry select adder because we only need one
XOR gate and one INV gate in each summation operation as
well as one AND gate and one OR gate in each carry-out
operation after logic simplification and sharing partial circuit.
Because of hardware sharing, we can also significantly
reduce the occurring chance of glitch. Besides, the
improvement of power consumption can be more obvious as
the input bit number increases. We simulated the power
consumption in the proposed area-efficient adder and the
conventional carry select adder with 4, 8, 16, and 32-bit
respectively in tsmc 0.18um CMOS technology.
CONCLUSION
In this paper, an area-efficient carry select adder is
proposed. By sharing the common Boolean logic term, we
can remove the duplicated adder cells in the conventional
carry select adder. In this way, the transistor count in a 32-bit
carry select adder can be greatly reduced from 1947 to 960.
Moreover, the power consumption can be reduced from
1.26mw to 0.37mw as well as power delay product reduced
from 2.14mw*ns to 1.28mw*ns. By retaining part of parallel
architecture of conventional carry select adder, we can still
maintain some competitiveness in speed.