23-07-2014, 02:50 PM
An Area Efficient, High Speed Novel VHDL
Implementation of Linear Convolution of Two
Finite Length Sequences Using Vedic
Mathematics
An Area Efficient.pdf (Size: 156.24 KB / Downloads: 43)
Abstract -
This paper presents a novel method of implementing
linear convolution of two finite length sequences (N×N) in
hardware using hardware description language (VHDL). The
proposed method uses modified design approach by replacing the
conventional multiplier by Vedic multiplier internally in the
implementations. The proposed method is efficient in terms of
computational speed, hardware resources and area significantly.
The efficiency of the proposed algorithm is tested by simulations
and comparisons with different design approaches using
XILLINX software. The presented circuit consumes less power
and has a delay of 17ns from input to output. The proposed circuit
is also modular, expandable and regular which provides flexibility
to form different number of bits.
I. INTRODUCTION
Many digital signal processing applications require
convolution operations for filtering of signals. The existing
methods of hardware implementation of linear convolution
sum affects the performance of DSP system because of
higher delay, area and power requirements. In this paper, a
novel method of computing discrete linear convolution is
using Vedic multiplication technique is presented. The
increased speed convolution algorithm in VHDL also
improves level of abstraction. The mathematical formula to
find linear convolution is fundamentally similar to URDHWA
TIRYAGBHYAM sutra in Vedic mathematics.
The organization of paper is as follows: Section II
introduces the method and properties of linear convolution.
Section III investigates Vedic mathematics and URDHWA
TIRYAGBHYAM sutra in detail. In section IV the circuit
implementations of proposed design are presented. Section V
presents the verification and results achieved. Finally the
conclusion is obtained.
CONCLUSION
In this paper, an optimized design for linear convolution is
presented. This design model has advavantage of fine tuning
depending on the requirement for enhancing the signal
processing model.This implementation also improves the
efficiency of the model design in terms of area and speed
requirements.The proposed system design is coded using
VHDL language and synthesized for FPGA products with
XILLINX 13.1 software. The proposed design is tested for
4×4 discrete convolution using ISIM simulator. The
proposed system saves 50% area and it takes 17 ns to
complete.The presented concept can be extended on N×N
discrete convolution. The modularity and reconfigurability of
FPGA makes the design compatible for future improvements.