27-12-2012, 06:24 PM
An Efficient Method for Detecting Delay Faults and Open Defects
An Efficient Method for Detecting Delay Faults.pdf (Size: 1.2 MB / Downloads: 49)
Abstract
Some open defects in VLSI circuits may cause delay faults,
and testing of open defects and delay faults remain difficult
problem. In this paper, we show that i) some open defects
cause delay faults and ii) those open defects and delay
faults cause variations in IDDT waveforms. We propose a
new IDDT testing method for detection of open defects and
delay faults. Our method exploits the phenomenon that an
open defect generates a local maximum in the IDDT
waveform. We present experimental results performed on
two test chips.
INTRODUCTION
IDDQ testing monitors quiescent power supply current.
It has been an effective method for testing short faults
[1]-[4]. Since open defects often do not lead to abnormally
high quiescent current, IDDQ testing may be ineffective for
detecting open defects. IDDT testing methods, which
observe instantaneous or mean values of transient power
supply current, have been proposed to replace or
complement IDDQ testing [5]-[8]. Sachdev et al. proposed
an IDDT testing method, which employs a current probe to
monitor transient current [7]. Min and Li proposed an IDDT
testing method based on measuring the mean value of
transient currents [8]. They showed that their proposed
method can detect open faults which cannot possibly be
detected by stuck-at fault testing or IDDQ testing methods.
PRELIMINARIES
IDDT is a transient power supply current which flows
into a circuit through VDD pin in the transient state of the
CUT. It is the sum of transient currents of individual gates
of the circuit. Transient currents of a CMOS inverter for
two different slopes of the input are shown in Figure 1. The
figure shows that as the slope of the input signal becomes
less steep, the transient current is delayed longer, i.e.,
RELATIOSHIPS BETWEEN OPENS, DELAY FAULTS, AND IDDT
We investigated relationships between open defects,
delay faults, and IDDT through simulation and present the
results in this section. Based on the simulation results, we
propose an IDDT testing method, which can be used to detect
some open defects and delay faults. So our method can
complement existing methods for detection of open defects
and delay faults. The circuit considered for the simulation
is a cascade of four identical CMOS inverters as shown in
Figure 4. It contains an open defect modeled as a resistor
Ropen between two nodes, IN2 and IN2*. The underlying
technology of the circuit is 0.6 μm n-well process. All
results presented in this section were obtained through
SPICE simulation.